Hello.
Now I'm designing a board like this.
CPU(ROOT/Up Stream) <-> XIO3130 <-> FPGA(End Point/Down Stream)
(The FPGA has PCIe IP.)
I wanna implement following both direction access.
(A) CPU(Master) -> FPGA(Slave)
(B) FPGA(Master) -> CPU(Slave)
I can access (A) direction already,
But I can't access (B) direction.
When accessing via XIO3130,
Do I need set some setting to XIO3130 for (B) direction access ?
(In my board, the setting for XIO3130 is default setting.)
