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DS250DF810 / about the input timing of REFCLK(CLK_CAL_IN)

Other Parts Discussed in Thread: DS250DF810

Hi,

Customer is considering DS250DF810. And they have some questions.Please let me know the details.

Q1

Are there time constraints between power up VDD and input 25MHz at CLK_CAL_IN?

Before power up VDD, could CLK_CAL_IN accept 25MHz?

Q2

Could the unused pins(RX*P,RX*N,TX*P,TX*N) be open?

Best Regards,

Kato