[TPS65982] configuration setting for DisplayPort

Fukui-san,

I think your statement is correct for the option which lists Pin Assignments A-B-C-D-E-F, but my proposed change would be slightly different.

Only the words Plug and Receptacle need to be flipped in both sentences to make it correct.

See this screen shot I took to illustrate my proposed change to the text for accuracy:

The option which lists Pin Assignments A-B-C-D-E-F should read "DFP_D Receptacle (or UFP_D Plug) Pin Assignments"

The option which lists Pin Assignments A-B-C-D-E- should read "UFP_D Receptacle (or DFP_D Plug) Pin Assignments"

As receptacles are more common, this is the more straightforward option and is listed first.

Fukui-san,

I have suggested a change to the text in the Tool, but I do not believe a typo will force a new version of the Tool to be released. I will confirm that the Text change is made to resolve the typo, and it will be reflected in the next planned release of the Tool (date not set yet.)

However, the most reliable option is to use the TPS6598X-CONFIG Tool with "Show Bitfield Ranges" Enabled and match the TPS6598X bits to the Bits of the spec you are working with.

• For any USB PD Config Register (for example, Tx Sink Capabilities = Reg. 0x33 or Tx Source Capabilities = Reg. 0x29), the TPS6598X Register follows the USB PD Specification exactly, bit-by-bit.
• For any Alt. Mode related configuration Register (for example, DisplayPort Capabilities = Reg. 0x51), the TPS6598X Register follows the specification exactly after the "SVID Enable" and "Mode # Enable bits", excluding RESERVED bits (for example, the VESA DP Alt. Mode spec Table 5-2)

In the VESA spec, Table 5-2 is named DisplayPort Cabilities and lists bits 23..0, where bits 15..8 = DFP_D Pin Assignments and bits 23..16 = UFP_D pin assignments.

In TPS6598X Register 0x51, is named DisplayPort Capabilities  where Bit 0 = DP SVID Enabled, Bit 1 = DP Mode 1 Enabled, and bits 7..2 = RESERVED. Therefore, Reg. 0x51 is equivalent to VESA Table 5-2 but shifted left by 8 bits. In other words, Bits 23..16 = DFP_D Pin Assignments and Bits 31..24 = UFP_D Pin Assignments (there are also a few extra trailing bits that are specific to the TPS6598X.)

Keep in mind that the UFP_D Pin Assignments bits do not allow Pin Assignment F (see Table 5-2 and Table 3-4: USB Type-C Receptacle UFP_D Pin Assignment Requirements), and bits 31..24 of Reg. 0x52 in the Tool clearly reflect that distinction.

Although we are continuously improving on and fact-checking the descriptions in the Config Tool, there are still a few typos or Registers that are difficult to understand. Thank you for pointing out this typo, and while we work on the correction please rely on the resemblance to the VESA DP Alt Mode spec for the register in question.

Furthermore, here is the text verbatim from the spec regarding the differences between Plugs and Receptacles with respect to DFP_D and UFP_D Pin Assignments:

"The DFP_U shall ensure that the UFP_U’s capabilities are consistent with its own capabilities,
taking care to note that a UFP_U that uses a USB Type-C Plug describes the pin assignments
supported for the corresponding receptacle (i.e., a UFP_D will describe the DFP_D pin assignments
to which it connects), whereas a UFP_U that uses a USB Type-C Receptacle describes its pin
assignments directly (i.e., a UFP_D will describe its own UFP_D pin assignments)."