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TLK1101E related question

Harini Ramanujam
Prodigy 635 points
Other Parts Discussed in Thread: TLK1101E, ONET8501P

Hi,

Can you please help clarify below issue for a customer?

In setting functions from a uC to communicate through the I2C interface (ONET8501P and TLK1101E), they will each acknowledge their own slave address, but then will hold down SDA line for the following 8 bits. The SDA line is then released for the 9th or acknowledge bit sending a NAK. I am using the same function to shift out both the slave address byte and the register address byte where the problem occurs. I have measured the clock L-H periods, rise-fall times- data and stop time setups etc.. and everything looks well within specs. The SCL is running at 70KHz.

 

  • 0
    TI__Expert 8915 points

    I don't understand the question.

    Is this still an issue?

    Alex.

  • 0 in reply to Alex Davidson
    Prodigy 50 points

    Alex helpfully clarified for me that the read transaction requres a "dummy write", also known as a repeated start condition, which is not uncommon for directing register reads from slaves. This information is nowhere in the 3-year-old datasheet so I am posting it here on E2E to save someone else the two days it took me to hunt this down.

    If you try to read following the datasheet, which indicates

    "The protocol for a data transmission is as follows:
    1. START command
    2. 7 bit slave address (0001000) followed by an eighth bit which is the data direction bit (R/W). A zero indicates
    a WRITE and a 1 indicates a READ.
    3. 8 bit register address
    4. 8 bit register data word
    5. STOP command"

    you will succeed (with appropriate ACKs) for writes. You can observe success by e.g. seeing the current consumption jump when your device is enabled. Data is MSB-first, like I2C should be.

    If your code is like mine (was at first), reads will ACK the address but NAK the register data word. Your handler should return with error due to the NAK. An example of a failed read from slave 0x10 (left-justified) address 0x02 is here. It appears the slave is returning 0x00 and then NAKing the transaction, but after thinking about it I guess it may just be that the TWI state machine clears its transmit holding register at the end of a transaction, and the new transaction is NAKed, but the TWI still shifts out the THR data causing SDA to be pulled low.

    The fix is to add the repeated start: first write the register you want to read, get ACK for slave address and ACK for register data word, then issue repeated start command (SDA goes low while SCL is high), then read one data byte, getting another ACK for slave address (plus read bit). You, the master, should/must NAK the read transaction to complete the bus cycle.

    Pictorially, this is: