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XIO2213B Interrupts

Marcin Wroblewski
Prodigy 40 points
Other Parts Discussed in Thread: XIO2213B

I know the XIO2213B does not support Message Signaled Interrupts, but does it support Legacy Interrupts (in-band messages) ?

Legacy Interrupts: In PCI Express, four physical interrupt signals (INTA-INTD) are defined as in-band messages. When the core needs to generate a legacy interrupt, it sends INTA-INTD message upstream which would ultimately be routed to the system interrupt controller.

From the XIO2213B datasheet:

3.4 PCI Interrupt Conversion to PCIe Messages
The bridge converts interrupts from the PCI bus sideband interrupt signals to PCIe interrupt messages.
Since the 1394a OHCI only generates INTA interrupts, only PCIe INTA messages are generated by the
bridge.

Is there any information you can provide on how to configure the XIO2213B evaluation board to generate the generate these interrupt PCIe messages ?

Thanks,
Marcin

  • 0
    TI__Guru* 76130 points
    Hello,
    The EVM does not have options to manually generate interrupts, they have to come from the 1394 interface.
    Regards
  • 0
    Guru 316690 points
    The board does not need any special programming; the PCI and 1394 drivers of your OS already handle the interrupts.

    What is the actual problem you're trying to solve?
  • 0
    Prodigy 40 points

    I'm using an operating system that supports only the PCI Express INTA (which is implemented using Assert and De-assert in-bound messages).   I'm also using the XIO2213B evaluation board, with a Firespy to generate 1394 traffic.   Everything is initialized correctly and I see the 1394 messages being DMAd to the host RAM, with the appropriate bits set in the OHCI IntEvent (0x80) register upon completion of the corresponding DMA.   I even see INTB and INTD messages from the XIO2213B if I continuously clear the asynchronous request TX bit via the OHCI IntClear register (0x84).     How do I get the XIO2213 to generate INTA, so the Bridge converts it to and INTA message, so my OS can process it ????

  • 0 in reply to Marcin Wroblewski
    Guru 316690 points
    The XIO2213B itself can generate only INTA messages.

    Which OS is this?

    Are there any bridges between the XIO and the root port? What are the device numbers of the devices on the secondary sides of all bridges?
  • 0 in reply to Clemens Ladisch
    Prodigy 40 points

    The OS is DDC-I Deos.

    The hierarchy of the bridges/devices is:

    PCIe1: Root Complex, x4 5.0 GT/s, regs @ 0xdf240000
      01:00.0     - 10b5:8619 - Bridge device (x4, 5.0 GT/s) - PCIe Switch
       02:03.0    - 10b5:8619 - Bridge device (x1, 2.5 GT/s) - PCIe Switch
        04:00.0   - 104c:823e - Bridge device (x1, 2.5 GT/s) - XIO
         05:00.0  - 104c:823f - Serial bus controller               - XIO
       02:05.0    - 10b5:8619 - Bridge device (no link)          - PCIe Switch (unused)
       02:07.0    - 10b5:8619 - Bridge device (x1, 2.5 GT/s) - PCIe Switch
        07:00.0   - 104c:823e - Bridge device (x1, 2.5 GT/s) - XIO
         08:00.0  - 104c:823f - Serial bus controller               - XIO
       02:09.0    - 10b5:8619 - Bridge device (x1, 2.5 GT/s) - PCIe Switch
        09:00.0   - 104c:823e - Bridge device (x1, 2.5 GT/s) - XIO
         0a:00.0  - 104c:823f - Serial bus controller               - XIO

  • 0 in reply to Marcin Wroblewski
    Guru 316690 points

    The XIO2213B 1394 controller always generates INTA signals.
    The XIO2213B PCIe/PCI bridges converts them into (De)Assert_INTA messages.

    The PLX bridge device converts INTA messages on the secondary side into INTB and INTD messages on the primary side. It is required to do this according to table 2-13 in section 2.2.8.1 of the PCIe 1.1 specification, which also says:

    Note that system software (including BIOS and operating system) needs to comprehend the remapping of legacy interrupts (INTx mechanism) in the entire topology of the system (including hierarchically connected Switches and subordinate PCI Express/PCI Bridges) to establish proper correlation between PCI Express device interrupt and associated interrupt resources in the system interrupt controller. The remapping described by Table 2-13 is applied hierarchically at every Switch. In addition, PCI Express/PCI and PCI/PCI Bridges perform a similar mapping function.

    If the OS does not follow this mapping, it is buggy.