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DM648 - PCI communication to XIO2001

Other Parts Discussed in Thread: XIO2001, XIO2000A

Hi,

maybe a very basic question...

I have a PCI device (XIO2001) connected to the DM648 PCI interface.

I think that the basic mechanism to communicate to a second PCI device is: move an "address window" to get access to a memory area of the second device. But how does the DSP know where to map this address window to get access to the XIO2001?

How can the DSP read for example the value of a config register of the XIO2001?

bye,

Thomas

 

  • You can only reach the configuration registers of the XIO2001 using type 0 configuration accesses. According to the XIO2001 data sheet (section 3.6, page 30), all type 0 configuration transactions are accepted by the bridge and never passed to the secondary bus.

    The DSP PCI has three proxy registers that are used to generate configuration read & write accesses: PCIMCFGDAT, PCIMCFGADR, and PCIMCFGCMD.  Keeping PCIMCFGADR[1:0] = 00b will ensure a type 0 configuration access is generated.

  • Hi Gus,

    thanks for your answer... 

    I tried to follow the description 'Configuration Read Transaction' in chapter 4.4.3 of spruel4b.pdf (DM648 PCI manual).

    PCIMCFGADR=0x00010000, 0x00010004, 0x00010008, 0x0001000C ...
    PCIMCFGCMD: TYPE=0, RD_WR=1, BYTE_EN=1 (is this correct? What is the meaning of this BYTE_EN?)
    reading PCIMCFGDAT after some nops returns the configuration values of the DM648 PCI interface.

    Currently I test using an EVM648 --> XIO2000A-EVM --> PC. Calling lspci returns the config memory for both devices:
    lspci -s 06:00 -x
    06:00.0 Signal processing controller: Texas Instruments Device b001 (rev 01)
    00: 4c 10 01 b0 16 01 20 02 01 00 80 11 08 40 00 00

    lspci -s 06:00 -x
    06:00.0 Signal processing controller: Texas Instruments Device b001 (rev 01)
    00: 4c 10 01 b0 16 01 20 62 01 00 80 11 08 40 00 00

    what I readback is:
    0xB001104C
    0x62200116
    0x11800001
    0x00004008

    so somehow swapped, but clearly the configuration of the DSP-PCI interface. All other values of PCIMCFGADR (I tried 0x00020000, 0x00040000...) return the value of PCIMCFGADR in PCIMCFGDA. How is the XIO addressed from the point of view of the DM648? Is there an example somewhere?

    bye,

    Thomas

  • Hi Gus,

    just to be sure... thats the system I use...:

    PC <---> PCIe <---> XIO2000A (later on XIO2001) <---> PCI <---> DM648 (EVM648)

    isn't DM648 connected to the 'secondary interface' of XIO?

    in the XIO manual, all 'configuration transaction' is 'from the point of view of the PCIe side: "PCI Express type 0 configuration register transactions always target the configuration space and are never passed on to the secondary interface."

    is the PCIe the 'secondary interface from the point of view of the DSP?

    Is an interaction/initialization required from the PC (PCIe side of XIO)? What if the card is powerd on without the PC (not even the BIOS) being booted? Will DM648 still be able to access XIO?

    bye,

    Thomas

  • You are right, I missed the fact that the config transaction must come from the PCIe side of the bridge.  I'm going to have this post moved to a forum that is more specifically targeted at the XIO2001.  You will get better support there.

  • is there anything else the DSP can access actively on the XIO2001?

    The reason why I want to do this is to debug a set of prototype cards - on which XIO seems to be inactive or faulty. If the card is inside a PCIe slot, it will prevent the PCs BIOS from booting. Apart from 'learning how things work' I want to access XIO somehow from the DSP side to debug this problem...

  • Thomas,

    All configuration accesses to the XIO2001 must occur from the PCIe side of the device.

     

    -DK

     

     

  • Hi DK,

    is there anything the DM648 can access on the PCI side in order to check if the XIO is basically alive? Or is there no way before the XIO gets configured from the PCIe side?

    Thomas

  • Thomas,

    The PCIe side of the device must be up and configured for the PCI side to work at all.

    -DK