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TCA9555 - the counterplan of error of bus access

Dice-K
Mastermind 7470 points
Other Parts Discussed in Thread: TCA9555

Hello,
I have two questions about TCA9555.

I connect TCA9555PWR and BR24T32-W by I2C.

The datasheet of BR24T32-W is this.

br24t32-w-e.pdf

The datasheet of BR24T32-W describes the counterplan of the error of bus access.
The page-16 describes that "Dummy Clock×14 + START+START+ Command Input".

Q1.
Is this counterplan no problem for TCA9555PWR?

Q2.
When the error of bus access occurred at TCA9555PWR, is this counterplan correct?
If it is not correct, please teach me the recommended method.

Regards,
Dice-K

  • 0
    TI__Expert 5140 points

    Hi Dice-K,

    To answer your questions on the "counterplan" please see below:

    Q1.

    Is this counterplan no problem for TCA9555PWR?

    When you say that if the counterplan will be a problem for TCA9555, I'm assuming that you are asking if this will damage the device or cause it to corrupt data across the I2C bus. This would be incorrect. From the looks of that datasheet, it looks as if it details a software reset for the slave device and how to reset it if there are issues. I don't see a problem with the operation of TCA9555 as this is common for slave devices to be reset.

     

    Q2. 

    When the error of bus access occurred at TCA9555PWR, is this counterplan correct?

    If it is not correct, please teach me the recommended method.

    I would say this is a correct plan. It is common for devices to be reset when there are errors on the bus.

     

    Thanks,

    Siby