error rate is big in loopback mode

guang shen

We are trying to do the RX electrical test with Lecroy PERT. After the loopback handshake, we put the PHY into loopback mode by:

txdetectrx/loopback:    1'b1
        txelecidle:    1'b0
        powerdown:  2'b00

then we use the PERT to send CP0, the error rate is about 2.0e-1, which is very strange. it is seems that the PHY is not in loopback mode.

if we use the PERT to send CP1, the error rate is about 4.0e-9, which is still a big value, but much better then CP0.

if we use the PERT to send CP2, there will be no error.

if we use the same test environment to test another PC host, there is no error. so we think the test environment should be OK.

over all, it seems that PHY works in a strange mode when we put it into loopback mode. Is there any extra configuration that we should do when setting PHY into loopback mode?

we found it on errata, that "Corrupted SKIPS returned to USB3 Loopback Master.." does it mean that if we want to pass RX electrical test, we have to implement external loopback in FPGA?

over 9 years ago

0 Elias Villegas M. over 9 years ago

TI__Guru* 76130 points

Hello,
Correct, the loopback should be implemented in the FPGA.
Regards

0 Mohsen over 8 years ago in reply to Elias Villegas M.

Prodigy 60 points

Hi Elias,

Can you please elaborate on the exact nature of the SKIPS error from the phy for this loopback issue? Is it the number of the SKIPS or the placement of them withing the BERT commands? We'd like to avoid the same errors since we need to design the loopback in the link layer.

Thanks,
Mohsen

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error rate is big in loopback mode