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sn65dsi84 in dual lvds output mode

Dimitris Tassopoulos
Prodigy 155 points
Other Parts Discussed in Thread: SN65DSI84

Hi Joel.


I've managed to get video output from the sn65dsi84. The test image works just fine and I'm also getting video output from glxgears in linux. The problem is that only the left half of the display outputs the video and the right half is just blank. Here there is a i2c dump of my registers.

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 35 38 49 53 44 20 20 20 01 00 85 28 00 01 00 00    58ISD   ?.?(.?..
10: 26 00 56 56 00 00 00 00 6c 00 03 00 00 00 00 00    &.VV....l.?.....
20: c0 03 00 00 00 00 00 00 20 00 00 00 14 00 00 00    ??...... ...?...
30: 0a 00 00 00 28 00 0f 00 28 00 0f 00 00 00 00 00    ?...(.?.(.?.....
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 f1 00 00 00 00 00 00 00 00 00 00    .....?..........
f0: 00 00 00 00 40 00 00 80 00 00 00 00 00 00 00 00    ....@..?........

I see that the R/O addresses 0x00-0x04 are referred to DSI85 and the IC I have here is sn65dsi84. I suppose that's nothing; they just share the same firmware.

Second, some observations I have during my tests. The display we're using is dual-lvds only. From the sn65dsi84 datasheet I've seen that when the flags in 0x10.6:5 are set to 0x01 and 0x18.4 = 0, then the chip is programmed to dual-lvds output. Also the datasheet on Table 9, says that when this is the case then the registers that control CHB (e.g. 0x22, 0x23, 0x26, 0x27, 0x2B, 0x2C etc) they need to be empty as the registers for CHA control the dual-lvds output.
 Actually I've also tried to fill the CHB registers with the same values as CHA, but it didn't make any difference.

Also, while experimenting I've seen that while in dual-lvds mode, if I change the resolution at registers 0x20-0x21 then the left half image responds to the changes and expands to the right side. If I keep rising the resolution then I can see image up to 0x0767 (1895p) and if add another pixel more then the screen goes blank, so I can't use 0x0780 (1080p) there. Also, as I've understand from the datasheet and DSI tools,  the 0x20-0x21 registers should have the half resolution (0x03C0 = 960p) when the dual lvds mode is set. Therefore, I can't explain the behavior of the chip. Do I do something wrong here?

The LCD panel's datasheet is here.

Regards,

Dimitris

  • 0
    TI__Mastermind 18655 points

    Hello Dimistris,

    Only the DSI85 has access to channel B video registers (sorrry for the confusion in your previous post).

    Since the DSI84 is working as single DSI Input to Dual-Link LVDS bridge it is required to program the length, in pixels (1920), of the active horizontal line in the register 0x20 and 0x21, the the HSync Pulse Width in 0x2c and 0x2d, the VSync Pulse Width in 0x30 and 0x31 and the Horizontal Back Porch in 0x34.

    The SN65DSI84 expects the GPU to provide video timing events and active pixel data (1920p) in the proper order in the form of a real-time pixel stream.

    The DSI input timing parameters MUST match the calculated value by the DSI Tuner tool(calculated based upon the DSI configuration and panel requirements). The DSI83 does not realign the timing. The line time presented in the DSI input should remain the same at the LVDS output(per the panel requirement). The mismatch of the timing may result in internal buffer underflow/overflow which typically flag the errors you are reporting(SOT and LLP error).

    For example:

  • 0 in reply to Joel Jimenez0
    Prodigy 155 points
    Hi Joel.

    Everything works fine. This is a great chip actually, great job. After I got used to it's setup and parameters, now I can say that it's simpler than I first thought.
    My problem was that I had to trim the pixel clock delay from dsi to lvds (reg 0x28). After some trimming there, everything works fine.

    Thank you for your support and your time!

    Regards,
    Dimitris