TLK110 Internal power-on reset

Seishin

Genius 4135 points

Hello,

When a single supply operation,what is the voltage level of AVDD33(or PFBOUT) an internal power-on reset is generated?

Best regards,
Seishin

over 9 years ago

0 Ross Pimentel over 9 years ago

TI__Mastermind 23675 points

Hi Seishin,

AVDD33 should be around 3.3-V.
PFBOUT should be around 1.55-V.

Kind regards,
Ross

0 Seishin over 9 years ago in reply to Ross Pimentel

Genius 4135 points

Hi Ross,

Thank you for your prompt reply.

I am sorry that my explanation was not enough.

I want to know the POR threshold voltage when the internal power-on reset function occurs.

Could you tell me?

Best regards,

Seishin

0 Ross Pimentel over 9 years ago in reply to Seishin

TI__Mastermind 23675 points

Hi Seishin,

I believe it is around 1.2-V, but let me verify.

Kind regards,
Ross

0 Seishin over 9 years ago in reply to Ross Pimentel

Genius 4135 points

Hi Ross,

Thank you very much.

I understand.

Best regards,
Seishin

0 Ross Pimentel over 9 years ago in reply to Seishin

TI__Mastermind 23675 points

Hi Seishin,

After looking into our files, the POR should be triggered around 1-V. There is a typical delay of 100ms though after this threshold is hit to ensure successful ramp to the final rail state.

Here is a basic process that goes on:

Supply Powered-up -> PHY detects 1-V threshold and initiates timer to delay 100ms until beginning internal processes -> Supply ramp to final state -> PHY latches in Hardware bootstrap settings and begins the process of enabling IOs

Kind regards,
Ross

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TLK110 Internal power-on reset