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I have a question about DS100DF410.

Other Parts Discussed in Thread: DS100DF410, DS110DF410

Can DS100DF410 load configuration via an external EEPROM without host device?

The system only contains a DS100DF410 and a EEPROM(AT24C08A).

The chip outside:

EN_SMB = Float for master mode

READ_EN: From high to low (CPLD to control the voltage change)

  • Hi Fly,

    Yes, this can be done. In Master Mode, the DS100DF410 will take control of the bus and load settings from the EEPROM slave device. Once done, the DS100DF410 will release control of the line. However, once the DS100DF410 loads its settings from the EEPROM, you will not have any other means by which to monitor or program the DS100DF410. At the least, I would recommend having header pins available to access the SMBus SDA/SCL lines in case debug is necessary.

    Regarding your choice of EEPROM, the AT24C08A should be fine, but usually we recommend an EEPROM capable of supporting up to 1 MHz, since it is possible that the DS100DF410 may drive the line at greater than 400 kHz. I recommend the AT24C08C instead.

    Regards,

    Michael
  • Hi Michael,

        Thank you very much for your detailed answer.

        I also have some questions about it 。 My system contains  one DF410 and one EEPROM  .As shown in figure 1.There is no  SDA and SDC signal(SDA and SDC is always keep high).

        Is it  can work normally?   I found this description in the  Datasheet,As shown in figure 2.Is it means I should give system a cpu (Mcu) to set its  register(0x05 ,bit7)?

                                 figure 1.System Diagram

                 figure 2.Datasheet

    Regards,

    Fly

  • Hi Fly,

    The description you have referenced is only relevant if you wish to exit EEPROM Master Mode before an EEPROM read has begun. There is no need to access Reg 0x05[7] if you have no desire to exit EEPROM Master Mode.

    Based on your situation, you will only need the EEPROM to have the correct hex file information loaded in beforehand. When the DS100DF410 starts up, it will wait until the READ_EN# pin goes low, after which the DS100DF410 will take control of the SMBus line and read its settings from the EEPROM. Once done, the ALL_DONE# pin will go low and the DS100DF410 is programmed. No additional writing to the DS100DF410 by an external MCU is required unless you wish to access the DS100DF410 afterwards for debugging or on-the-fly programming needs.

    Regards,

    Michael
  • Hi Michael,

    Thank you again for your reply!

    It is my  fault  to  measure  SDA/SDC signal . Now,DF410can load something from EEPROM ( EEPROM is work on ) . However , SFI signal  didn't output .

    ------------------------------------------------------------------------------------------------------------------------------------------------

      CPU   configuration  file:

    ----------------------------------------------------------------------------------------------------------------------------------------------

    {0x31, 0x40}, /* */
    {0x15, 0x35}, /* */
    {0x2F, 0x04}, /* enable divider for 1, 8 */

    {0x36, 0x31}, /* enable ref-mode-3 */

    {0x60, 0x00}, /* Set ppm value (LSB) for group0 1.25Gbps 10GHZ

    {0x61, 0xB2}, /* Set ppm value (MSB) for group 1.25Gbps 10GHZ

    {0x62, 0x90}, /* Set ppm value (LSB) for group 10.3125Gpbs

    {0x63, 0xB3}, /* Set ppm value (MSB) for group 10.3125Gpbs

    {0x3a, 0x00}, /* Fixed EQ for /8 rate, 1.25Gbps. EQ=1db@500MHZ

    {0x64, 0xFF},

    {0x0A, 0x1C}, /* Set the reset bit for the CDR */
    ----------------------------------------------------------------------------------------------------------------------------------------------

    //Wait for 1 second//

    ----------------------------------------------------------------------------------------------------------------------------------------------
    {0x0A, 0x10}, /* unset the reset for the CDR */

    {0x2D, 0x82}, /* set vod to 700mv, for test only */ 
    ----------------------------------------------------------------------------------------------------------------------------------------------
    ----------------------------------------------------------------------------------------------------------------------------------------------
    I have used SigCon to translate CPU configuration file into image (set2_1 . Hex ) . 
    I don'tknow this file whether there is any problem . Can you help me to translate CPU configuration file intoimage ? and I can compare them .

    I used scope and Logic analyzer   measure the SDA and SDC ,we found the DF410 only read a part of configuation(hex file :Read from start to 394100) from the EEPROM (AT24C08D).

    Could you pls help to check why the DF410 not read the whole configuation.()

    You can use this tools to open file(untitled1.logicdata) .

    Logic analyzer pic :

     

    Regards,

    Fly

  • This is hex file:

    :2000000070001000330000000000000000000000000000000000000000000000000000002D
    :200020000000000000000000000000000000000000000000000083C93693A20818006AF48B
    :200040006D230C91C4000033003941008204621F8F99000080004104100200A000C30C107D
    :20006000543018242220A81194A32C3215D75A5D756665A9402CA42CFFE90101000000007E
    :20008000000000000000000000000000000000000000000000000000000000000000000060
    :2000A000000000000000000000000000000000000000000000000000000000000000000040
    :2000C000000000000000000000000000000000000000000000000000000000000000000020
    :2000E000000000000000000000000000000000000000000000000000000000000000000000
    :200100000000000000000000000000000000000000000000000000000000000000000000DF
    :200120000000000000000000000000000000000000000000000000000000000000000000BF
    :2001400000000000000000000000000000000000000000000000000000000000000000009F
    :2001600000000000000000000000000000000000000000000000000000000000000000007F
    :2001800000000000000000000000000000000000000000000000000000000000000000005F
    :2001A00000000000000000000000000000000000000000000000000000000000000000003F
    :2001C00000000000000000000000000000000000000000000000000000000000000000001F
    :2001E0000000000000000000000000000000000000000000000000000000000000000000FF
    :200200000000000000000000000000000000000000000000000000000000000000000000DE
    :200220000000000000000000000000000000000000000000000000000000000000000000BE
    :2002400000000000000000000000000000000000000000000000000000000000000000009E
    :2002600000000000000000000000000000000000000000000000000000000000000000007E
    :2002800000000000000000000000000000000000000000000000000000000000000000005E
    :2002A00000000000000000000000000000000000000000000000000000000000000000003E
    :2002C00000000000000000000000000000000000000000000000000000000000000000001E
    :2002E0000000000000000000000000000000000000000000000000000000000000000000FE
    :200300000000000000000000000000000000000000000000000000000000000000000000DD
    :200320000000000000000000000000000000000000000000000000000000000000000000BD
    :2003400000000000000000000000000000000000000000000000000000000000000000009D
    :2003600000000000000000000000000000000000000000000000000000000000000000007D
    :2003800000000000000000000000000000000000000000000000000000000000000000005D
    :2003A00000000000000000000000000000000000000000000000000000000000000000003D
    :2003C00000000000000000000000000000000000000000000000000000000000000000001D
    :2003E0000000000000000000000000000000000000000000000000000000000000000001FC
    :00000001FF

    :2000000070001000330000000000000000000000000000000000000000000000000000002D
    :200020000000000000000000000000000000000000000000000083C93693A20818006AF48B
    :200040006D230C91C4000033003941008204621F8F99000080004104100200A000C30C107D
    :20006000543018242220A81194A32C3215D75A5D756665A9402CA42CFFE90101000000007E
    :20008000000000000000000000000000000000000000000000000000000000000000000060
    :2000A000000000000000000000000000000000000000000000000000000000000000000040
    :2000C000000000000000000000000000000000000000000000000000000000000000000020
    :2000E000000000000000000000000000000000000000000000000000000000000000000000
    :200100000000000000000000000000000000000000000000000000000000000000000000DF
    :200120000000000000000000000000000000000000000000000000000000000000000000BF
    :2001400000000000000000000000000000000000000000000000000000000000000000009F
    :2001600000000000000000000000000000000000000000000000000000000000000000007F
    :2001800000000000000000000000000000000000000000000000000000000000000000005F
    :2001A00000000000000000000000000000000000000000000000000000000000000000003F
    :2001C00000000000000000000000000000000000000000000000000000000000000000001F
    :2001E0000000000000000000000000000000000000000000000000000000000000000000FF
    :200200000000000000000000000000000000000000000000000000000000000000000000DE
    :200220000000000000000000000000000000000000000000000000000000000000000000BE
    :2002400000000000000000000000000000000000000000000000000000000000000000009E
    :2002600000000000000000000000000000000000000000000000000000000000000000007E
    :2002800000000000000000000000000000000000000000000000000000000000000000005E
    :2002A00000000000000000000000000000000000000000000000000000000000000000003E
    :2002C00000000000000000000000000000000000000000000000000000000000000000001E
    :2002E0000000000000000000000000000000000000000000000000000000000000000000FE
    :200300000000000000000000000000000000000000000000000000000000000000000000DD
    :200320000000000000000000000000000000000000000000000000000000000000000000BD
    :2003400000000000000000000000000000000000000000000000000000000000000000009D
    :2003600000000000000000000000000000000000000000000000000000000000000000007D
    :2003800000000000000000000000000000000000000000000000000000000000000000005D
    :2003A00000000000000000000000000000000000000000000000000000000000000000003D
    :2003C00000000000000000000000000000000000000000000000000000000000000000001D
    :2003E0000000000000000000000000000000000000000000000000000000000000000001FC
    :00000001FF
    

  • Logic analyzer file:untitled2.rar

  • Good night~
  • Hi Fly,

    I examined the .hex file you generated and everything seems to make sense to me. I do not believe there is anything wrong with the configuration. I am not sure why the EEPROM read is not completing. I would expect the EEPROM to complete loading into the DS110DF410 based on what you have, regardless of whether the programmed values for each register bit is correct or not.

    I do have questions about your desired setup:

    1. Could you share a schematic of your setup and whether there is anything else connected to the SMBus line that could be interfering?

    2. Have you verified that, in Slave Mode, the CPU configuration you have programmed into the DS110DF410 works?

    3. Are you using a DS110DF410? Your posts mention the DS100DF410, but if you are using a DS100DF410, there is no purpose in programming Reg 0x60-0x64, since the only data rates that will be locked by default is 10.3125 Gbps and 1.25 Gbps. There would therefore be no reason to set the data rate. Are you definitely using the DS100DF410?

    4. Is there any way to access the ALL_DONE# pin to see if it is pulling low? I'm curious to see if somehow the logic analyzer is signaling a NAK, but the DF410 is signaling that it successfully read the EEPROM contents anyway. I'd also try loading the EEPROM without the logic analyzer attached and then measure the ALL_DONE# pin output to see if it goes low.

    Regards,

    Michael
  • Hi Michael

    1.I upload the schematic of my setup and nothing connected to the SMBus line.(Only EEPROM).(file:SCHEMATIC1 _ 07_SFI_Repeater.zip)

    2.This step is fine .It is DS100DF410  not DS110DF410 .

    3.I sure it is DS100DF410 and I upload it's pic.In Slave Mode,it is  the CPU configuration.  I have a question to the CDR.(This is the only difference This is the only difference  CPU configuration(In Slave Mode)  and .Hex file (In Master Mode).)

    In Slave Mode ,CPU can program DS100DF410  Reg 0x0A (0x1C).Is it necessary to program  Reg  0x0A?If it is necessary ,what should I do?

    ------------------------------------------------------------------------------------------------------------------------------------------------

      CPU   configuration  file:

    ----------------------------------------------------------------------------------------------------------------------------------------------

    {0x31, 0x40}, /* */
    {0x15, 0x35}, /* */
    {0x2F, 0x04}, /* enable divider for 1, 8 */

    {0x36, 0x31}, /* enable ref-mode-3 */

    {0x60, 0x00}, /* Set ppm value (LSB) for group0 1.25Gbps 10GHZ

    {0x61, 0xB2}, /* Set ppm value (MSB) for group 1.25Gbps 10GHZ

    {0x62, 0x90}, /* Set ppm value (LSB) for group 10.3125Gpbs

    {0x63, 0xB3}, /* Set ppm value (MSB) for group 10.3125Gpbs

    {0x3a, 0x00}, /* Fixed EQ for /8 rate, 1.25Gbps. EQ=1db@500MHZ

    {0x64, 0xFF},

    {0x0A, 0x1C}, /* Set the reset bit for the CDR */
    ----------------------------------------------------------------------------------------------------------------------------------------------

    //Wait for 1 second//

    ----------------------------------------------------------------------------------------------------------------------------------------------
    {0x0A, 0x10}, /* unset the reset for the CDR */

    {0x2D, 0x82}, /* set vod to 700mv, for test only */ 
    ----------------------------------------------------------------------------------------------------------------------------------------------
    ----------------------------------------------------------------------------------------------------------------------------------------------

    4.Yes , I have measured the ALL_DONE and ALL_DONE has been pulled low . It should havefailed , because no signal output .

     I have tried it , but ALL_DONE# pin is low .

    .

    SCHEMATIC1 _ 07_SFI_Repeater.zip

    Regards,

    Fly

  • Hi Fly,

    Thanks for the information, and sorry for the delay. I recently reviewed the schematic, and I am curious about the resistor values you used for the address lines. These values should be tied with a 1k to VDD or 1k to GND. Right now, I see that they are 4.7k resistors. Please replace with 1k resistors to assure proper operation.

    Before we address DS100DF410 device settings in Slave Mode, I realized another thing that may help, and I think this may be causing the EEPROM to load incorrectly.

    I noticed your address AD[3:0] is set to 1010'b. The EEPROM address map headers are hard-coded such that the first address map header implies where the EEPROM data is for a device with AD[3:0] = 0000'b (that is, Address 0x30). The next address map header implies where the EEPROM data is for a device with AD[3:0] = 0001'b, and so on. Since your address map header in your hex file is located immediately after the base header bytes, it will try to load to a device located at Address 0x30. Unfortunately, your device is located at Address 0x42. This concept is explained in more detail in our 25-28G EEPROM app note: http://www.ti.com/lit/an/snla244/snla244.pdf

    There are two options to fix the issue:

    1. Leave your EEPROM .hex file as is. Then change the resistor values for the AD[3:0] address pins. If you tie all the address pins to GND with a 1k resistor so that AD[3:0] = 0000'b, the EEPROM should load correctly.

    2. Leave your device address AD[3:0] = 1010'b (Address 0x42), you must move your address map header information (0x003300) to the 10th address map header location. I have done this for you in the attached .hex file: https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/set_5F00_2_5F00_1_5F00_AD1010.hex

    Please try one of the two options and let me know if the values you are reading back from your CPU afterwards makes sense.

    Regards,

    Michael

  • Hi Michael

    My configration file is a little problem(DS100DF410).My EEPROM is AT24C08D and  I used  sigcon to  generate HEX file.I2C communication with different problems.

    Can you give me only a device configuration files(Image).

    Regards,

    Fly

  • Hi Fly,

    I took the hex file I generated and loaded it into SigCon Architect to double-check with the CPU configuration file values you are using. They look fine to me. Here is the saved .cfg file I viewed: DS100DF410_Test.cfg

    Regarding your question about CDR reset where you set Reg 0x0A[3:2] = 11'b and then 00'b, this step is helpful but not necessary to get the retimer to achieve lock. This CDR reset step is usually recommended in order to assure that the internal state machine can achieve lock from a known state.

    Before we begin debugging whether the register bits are all correct in your settings, I suggest performing a debug by modifying your setup so that you are using one of the two suggestions in my previous post. Afterwards, you can use SigCon Architect to read back the configuration in slave mode and see if the device register values are correct as expected. Once we know that the DS100DF410 is reading the EEPROM correctly, we can then begin to address the SFI output issue.

    Thanks,

    Michael

     

  • Hi Michael

    I do as you say to change some Settings.I have a few problems.

    1.I used my SigCon to generate hex file and DF41 always read not accurate configuration data;

    2.I used your  hex file downloaded to the EEPROM and DF410 can accurately read the configuration data, but  DF410 output  nothing.

    3.I compared the (Datasheet) the default value of the register and (SigCon) the default value of the register and I found some different things. (I didn't set those  registers).

    File :different.rar

    4.I found another problems of SigCon software.It is not reversible, when I use SigCon modify your hex file.(when i modify EEPROM>256? and common channel or Enable CRC, If I choose Add map enable ,Add 0x4  always is 0x33)

    Can you give me your software download address

    different.rar.

    You can see the changes in fig. 1,fig.2,fig.3

     fig.1

     fig.2

     fig.3

    Regards,

    Fly

  • Hi Fly,

    See my inputs below:

    1.I used my SigCon to generate hex file and DF41 always read not accurate configuration data;

    2.I used your  hex file downloaded to the EEPROM and DF410 can accurately read the configuration data, but  DF410 output  nothing.

    The result you observed with Michael's hex file is encouraging. To understand why "DF410 output nothing" I will need to know more about your setup and what you are trying to do.

    • For the retimer channel in question, what is the input pattern and data rate you are using?
    • What settings are you trying to configure on the retimer that are different from default (e.g. rate/subrate, VOD, adapt mode, etc)

    3.I compared the (Datasheet) the default value of the register and (SigCon) the default value of the register and I found some different things. (I didn't set those  registers).

    See my input to item 2 above.

    4.I found another problems of SigCon software.It is not reversible, when I use SigCon modify your hex file.(when i modify EEPROM>256? and common channel or Enable CRC, If I choose Add map enable ,Add 0x4  always is 0x33)

    Don't understand this question. need more clarification.

    Can you give me your software download address

    Go to the website below:

    www.ti.com/.../sigconarchitect

    Cordially,

    Rodrigo Natal

    DPS Applications Engineer

  • hi Michael,

    This issue is still pending now, can you support one DS100DF410EVM to me? I will help our customer to close this issue next week.

    My address:
    Texas Instrument Semiconductor Technologies (Shanghai) Co., Ltd
    32F China Fortune Tower, 1568 Century Avenue, Shanghai, 200122
    Jack Li
    86-21-2307 3302

    Regards,
    Jack
  • Hi Jack,

    I will get you in touch with our marketer to determine whether we can support this request. Since this EVM is already in the eStore, it will be easier for us to use the eStore ordering to send an EVM in this situation. I will send an e-mail to you separately.

    Regards,

    Michael