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SN65LVDS104 Fail Safe Enable

Steve Widener
Genius 11010 points

The subject part includes a Fail-Safe feature.  Page 14 of the datasheet (just above Figure 25) says, “The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage.”

 

Is the output only driven to the high-level if the applicable EN pin is in the high state (i.e. a given output only goes high in fail-safe mode if that output is enabled).

  • 0
    TI__Genius 11280 points
    Hello Steve,
    Regarding to your question (Is the output only driven to the high-level if the applicable EN pin is in the high state?) the answer is yes.

    Regarding the conection between the FPGA and LVDS104, if the FPGA is the output you have two options at least:
    a) The FPGA output is differential. Use the circuit of the figure 25.
    b) The FPGA output is LVTTL. Use the circuit of the figure 26(adapted to 2.5v).


    If the FPGA is the input you must to add a 100 ohm differential resistor at the FPGA end.

    Regards,
    Gerardo