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DSI84 LVDS output clock missing

Peter Chen(ICP_FAE)
Intellectual 2480 points

customer report that the LVDS output clock missing after 500 times power on-off stress testing.

any idea about the issue report?

  • 0
    TI__Mastermind 18655 points
    Hello Peter,

    As far as I know, there have been no similar reported cases.
    Please, have the customer to check the error reporting registers when the issue occurs.
    Additionally, a device swap is needed to see if the failure follows the device. What is the failure rate (# of units failing/# of units tested)?

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 90 points

    the failure rate about 3/500

  • 0 in reply to Hilary Tsai
    TI__Mastermind 18655 points

    Hello Hilary, 

    Do you have any update on this?

    • Please, have the customer to check the error reporting registers when the issue occurs. 
    • Additionally, a device swap is needed to see if the failure follows the device

    Regards

  • 0 in reply to Joel Jimenez0
    Prodigy 90 points

    Hi joel:

    sorry for error information, it is no data output not no clock out.

    I found that the same issue is also asked by hiker.

    https://e2e.ti.com/support/interface/digital_interface/f/130/p/535385/1950019#1950019

    However, I the dsi83 datasheet 

    For clock lock and unlock. I am confused.

    The default vale is 1 , I am not clear that if log show 0x01,Dose it mean  lock or unock? 

  • 0 in reply to Hilary Tsai
    TI__Mastermind 18655 points

    Hello Hilary,

    As the datasheet states, the PLL_UNLOCK bit is set whenever the PLL Lock status transitions from LOCK to UNLOCK. It is a known behavior that PLL_LOCK may be set during the initial sequence. Therefore, you have to check if this bit is being set back to 1 after it is cleared (write 1). if  you continue detecting the PLL_UNLOCK error, the input CLK is likely having a signal integrity issue.

    As per my understanding, the customer is using the DSI CLK as the clock source, therefore, it must be HS continuous as described in the datasheet.

    I would also check that the power rails have the correct voltage levels.

    Could you provide more details on the steps they are following to get the failure? I mean, power on and power off procedures. 

    Regards

  • 0 in reply to Joel Jimenez0
    TI__Intellectual 2480 points
    2 finding below:
    1) according to table 2 of datasheets, After power is applied and stable on DSI83, all DSI input lanes including DSI CLK(DA × P/N, DB x P/N) must be driven to LP11 state. Is there any side s effect if it does not driven to LP11 to DSI83? I knew driven to LP11 on DSI83 is must when power ramp up.
    2) if showing the white screen error, the register show value 0x81 in register 0xE5. according to DSI83 datasheets, it looks like HS/VS sync up problem.
    BTW, there is no white screen error, if goes with DSI83 internal LVDS test pattern generator(register show value 0x01 in register 0xE5).
    => Questions: is the DSI device PLL lock or not in 0x01 and 0xE5?