TLK105 / TLK106 in Ethercat-network doesn't start at temperatures over 35°C

Hi Karl,

The TLK105 needs to have a reference clock active when the power up occurs. It seems like you may be having an issue with reference clock timing, especially if you can recover the phy using a reset pulse.

Can you scope the XI and the single supply power up, and RESET line?

I'd like to graphically see the timing you have described.

Best Regards,

Hi Rob,

good idea, but this seems not to be the problem.
The clk ist stable 80ms before the reset goes high.
On te other side, the clk is a output of the ethercat-device and is connected parallel to the 3 TLK106. if i warm up one of them, only this one doesn't start.

best regards

Karl

Hi Karl,

Is the image above of a unit that is not working after power-up, but is after the reset pulse?

Reason why i ask is that the PHY does appear to be booting up correctly because the PFB voltage is indicating proper configuration.

Can you send me a schematic for review?

Kind regards,
Ross

Hi Ross,

the image ist exactly the same when the phy starts after reset or after 2nd reset. The small voltage drop on PFB is always 80ms after the 1st reset. The clk is  also stable before reset goes high. The LED_LINK stays high, when the phy doesn't start. otherwise it goes low.

Next i will try to get access via the management-interface and make a softwarereset, maybe this helps.

in the attached schematics all Signals on the left side go directely to the Ethercat-device.

kind regards

Karl

Hi Karl,

Do you have TX_CLK connected?

Also, do you have a pull-up on MDIO pin?

Regarding the behavior you observe, when you say it is not responsive, does this mean you can read the registers or that the PHY does not link and pass packets?

Do you see link pulses or MLT-3 signaling when the issue occurs? Trying to just figure out what exactly you are seeing.

Kind regards,

Ross

Hi Ross,

A 2k2 pullup is on the MDIO pin,
On MDC and MDIO i have never seen any signals.
I tried to access the PHY-registers via the ET100 and the microcontroller in front of it, but without success.

The TX_CLK is not connected,
when the PHY is running i see the 25MHz Clk on the TX_CLK pin,
when i remove the ethernet cable, there are 2,5MHz, but when the PHY doesnt start i see 1,25MHz
and on the TX-line are strange pulses with about 4kHz

.

kind regards

Karl    

Hi Karl,

Are you trying to use RMII or MII operation? 

For MII you must connect TX_CLK.

The image is of a link pulse and this is a good sign that the PHY is powering up and sending out the proper signaling.

Also, the PHY is not the managing device in a MDIO/MDC connection, it is the ET that is responsible for generating the MDC and pinging the PHY. If the ET is not doing that then the PHY will not drive the MDIO.

Can you confirm what configuration you want the PHY to be in:

1. Speed?

2. MAC IF?

3. Straps?

Kind regards,

Ross

Hi Ross,

the ET1100 uses MII-interface,100MBit full  duplex, 25MHz Clk.
The TX-Clk-pin isn't used in this application

The datasheet of ET1100 says:
Since ET1100 and the Ethernet PHY share the same clock source, TX_CLK from the PHY has a fixed
phase relation to TX_ENA/TX_D[3:0] from the ET1100. Thus, TX_CLK is not connected and the delay
of a TX FIFO inside the ET1100 is saved. The phase shift between TX_CLK and TX_ENA/TX_D[3:0]
can be compensated by an appropriate value for TX Shift, which will delay TX_ENA/TX_D[3:0] by 0,
10, 20, or 30 ns.

i have checked this: the setup- and hold-times from TX-CLK to TX-D are ok, Data changes at the falling edge of TX-Clk.

The management-if is really not used by the ET1100 in standard application, its only for diagnostic purposes

what do you mean with "Straps"?

kind regards

Karl

Hi Karl,

Thank you for the scope shot, it is quite helpful. I still believe you are experiencing a start-up timing issue. The TLK106 device resets on the falling edge of the RESET signal OR at power on (AVD33 rail ramping up). In the scope shot, XI is not present at the initial reset due to power on. The TLK does not receive a reset with XI stable until the 2nd reset pulse.

Holding the RESET line low until XI becomes stable does not satisfy the TLK106's requirement for reference clock stability, as you are observing. Please apply a RESET pulse after XI and AVDD33 are stable IF XI is not stable when AVDD33 initially ramps up.

Best Regards,

Hi Rob,

i understand what your ideas are. But this would be the first device i used on a board which needs a edge on the reset-line.  Every controller, peripheral etc. has a static reset, which is active, as long as the input is low. 
And the datasheet of the TLK says:
"The TLK10x includes an internal power-on-reset (POR) function, and therefore does not need an explicit
reset for normal operation after power up."

Clock and power are stable long before the reset goes high. Everything is ok, as long as we are below 38°C.

I wonder, that no one had ever this problem and we have it on 2 different boards with 2 different devices (TLK105 and TLK106) and we use it in a standard mode.

Best regards
Karl