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SFP+ interface

Julian Martin50
Prodigy 110 points
Other Parts Discussed in Thread: DS125BR820, DS110DF410, TLK10031, DS110DF111

Hello,

I´m not much into Ethernet so maybe I´m stating something wrong. I have the following question:

I´m designing a test board for a FGPA board. The FPGA has SFP+ over backplane and I´d need to connect this bus to a SFP+ connector. Is it necessary to interface this bus with a transceiver/PHY/CDR or can I just place a SFP+ connector with its cage directly to this bus lines?

On the other hand, is there any documentation that could bring some light to me on this topic?

Thanks in advance for your answers.

J

  • 0
    TI__Mastermind 23675 points
    Hi Julian,

    I would suggest you contact the high speed signal group. SFP+ is for 10Gbps speeds and our PHYs are for 10/100/1000Mbps.

    Kind regards,
    Ross
  • 0 in reply to Ross Pimentel
    TI__Mastermind 29655 points

    Hi Julian,

    Sorry for the delay. If you could share a block diagram of what you are considering, it will help us understand whether to recommend a signal coniditioning device or not.

    It is up to you whether you want to use a signal conditioning device like a redriver or retimer near the SFP+ connector, but it is not always necessary. Typically we see devices like our redrivers with EQ gain (for example, DS125BR820) or retimers with EQ + CDR + DFE (for example, DS110DF410) used near the SFP+ connector or in active cables that connect to the SFP+ cage. In the example below, the DS125BR820 is used to connect to a QSFP+ cage:

    The choice of whether a signal-conditioning device between FPGA and SFP+ connector is up to you. If the distance between FPGA and SFP+ connector is relatively minimal and attenuation or jitter effects are minimal, then you may not need to add an additional device between your FPGA and SFP+ connector. However, in most cases, using signal conditioning devices like redrivers or retimers adds significant improvement to the system performance and robustness against bit errors.

    A good resource for viewing how signal conditioning devices are used in SFP+ scenarios is detailed in the following app notes: 

    http://www.ti.com/lit/an/snla225/snla225.pdf

    http://www.ti.com/lit/an/snla226/snla226.pdf

    Thanks,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 110 points

    Dear Michael,

    thank you very much for your answer.

    the basic diagram of what I need to do is in the picture below. It is basically a FPGA with SFP+ transceiver. SFP+ bus will be routed through the PCB and connected through two VPX connector to another PCB where it will need to be connected to a cable on the edge of the card. I understand a CDR is necessary as there are several physical interfaces in the signal path so signal must be conditioned/corrected/recoveured before the edge connector.

    It wold be great if, instead of SFP+ connector the edge connector could be a 10GBASE-T (copper RJ45 Cat6 or higher). Could this be possible using the right phyceivers or similar?

    Thank you in advance for your answer.

    Best,

    J

  • 0 in reply to Julian Martin50
    TI__Mastermind 29655 points
    Hi Julian,

    Sounds like a DS110DF410 may be useful for you before you reach the edge of the card.

    Unfortunately, I am not aware of an IC other than some form of FPGA/ASIC that will be able to perform conversion from serial SFP+ to 10GBASE-T. We usually support applications where the data is transmitted on an NRZ differential pair. There are also solutions for aggregating and de-aggregating from XFI to XAUI using devices such as the TLK10031 (supported by another group).

    From a quick Google search, it seems like converter boxes exist for this type of translation from 10 GbE SFP+ to 10GBASE-T, as opposed to a single-chip solution.

    Regards,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 110 points

    Dear Michael,

    thank you very much for your answer.

    I have another question:

    The FPGA will also have a XAUI interface that will be routed in the same way the SFP+ bus is routed. I would like to know:

    1) Can XAUI be routed straight forward without transceiver/driver/buffer from the FPGA to the connector of the PCB2? Would it be better to use 10GBASE-KX4? What device would you recomend?

    2) Is there any possible solution to connect this XAUI bus to a connector and connect to a RJ45 Cable or Fibre? what device would you recomend?

    Thank you in advance for your answer.

    Best,

    J

  • 0
    TI__Mastermind 43795 points

    Hi Julian,

    It sounds like the FPGA is rated to drive an SFP+ connector.  So the cage and connector could be directly attached together via traces on PCB1 and PCB2.  For more information you can reference SFF-8431.  The biggest issue will be if the combination of PCB1+2 will represent a "compliant" channel.  See SFF-8431 Appendix A for more information.  The maximum loss is about 6 dB so it doesn't take much length to go beyond this limit.  For situations where it is not possible to keep the total channel compliant, many customers have used the DS110DF111 retimer to redrive a nice clean signal into the SFP cage connector.

    Hope this helps,

    Regards,

    Lee