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TMDS171/TMDS181 3-level Logic Interface

Other Parts Discussed in Thread: TMDS181, TMDS171

Hi,

The 3-level logic interface is applied for the pins of PRE_SEL, EQ_SEL/A0, TX_TERM_CTL and SWAP/POL.
I understood that these pins should be strapped to GND through 65kΩ if setting the logic low, be strapped to VCC through 65kΩ if setting the logic high.
So, why should 65kΩ resistor be applied as the pull-up or pull-down resistor ?
Could you please tell us that reason including the internal circuits ?

Best regards,
Kato