DP83867ISRGZ delay setting

Hi, Rob-san,

Thank you for your reply.

I'm sorry I could not exactly understand following meaning.

>The setting of the RGMII_TX/RX_CLK_DELAY bit is dependent on the strap options set in point 2 of your post.

Did you mean that user can set clock delay only using register setting ?

In addition, I noticed below.

So, I guess that reviced point of datasheet may be

1. Delete strap setting (Table 9. RGMII Transmit Clock Skew Details)

2. Delete following highlighted sentence.

Is my understanding correct ?

(If possible, could you please share draft version of datasheet in order not to misunderstand ?)

Best Regards,

Machida

Hi Machida-san,

Your understanding of the strap for RGMII delays using the DP83867 is not completely correct.  

">The setting of the RGMII_TX/RX_CLK_DELAY bit is dependent on the strap options set in point 2 of your post.

Did you mean that user can set clock delay only using register setting ?

In addition, I noticed below.  I think that MODE 5-8 can NOT be set by using strap setting. Because, according to the datasheet, user can set MODE only from 1 to 4."

Modes 1 to 8 in Table 9 do not refer to the strap pin modes 1 to 4.  The mode # in table 9 is only for reference and the way you enter the modes in table 9 is to set the CLOCK SKEW bits using strap pins.  

For example, I have put the following diagram together illustrating how to use MODE 6 (this is more accurate to say "configure TX clock skew to 3.5ns) for TX delay.

See that in order to set MODE 6 TX delay, the customer would need to use 2 strap pins to set the appropriate bits.  The bits in Table 9 are color coordinated to indicate which bits need to be set on the strap pins.

Depending on the delay set in the two straps in the illustration, the bits for RGMII_TX_DELAY_CTRL/RGMII_TX_CLK_DELAY will change.

Best Regards,

Hi Rob-san,

Thank you for your reply.
I understood relatationship b/w Table9 and Table7.

However, I would like to know below.

The dependency of this bit on a strap will be updated in the next DS revision.

Could you tell me how you add dependency of this bit on a  strap ?
(I understand that depending on strap setting, user can set RGMII_TX/RX_CLK_DELAY bit to "0".)

Best Regards,

Machida

Machida-san,

In the register table's default value, the word "Strap" is put in place of 0 or 1. This indicates the default value will be set based on the strap mode used.

The default value currently in the datasheet is RGMII_TX_CLK_DELAY = 0 and this is true if you strap to mode 5 in table 9. In all other modes, RGMII_TX_CLK_DELAY = 1. This means RGMII_TX_CLK_DELAY bit is dependent on a strap.

Best Regards,

Hi Rob-san,

Thank you for your reply.

I understood which point TI will change.

In addition, I have following two questions.

* Does TI update same change for RGMII_RX_CLK_DELAY bit ? (You mentioned only TX side, so i want to check it just in case.)

* Does TI update same change for datasheet of DP83867IR (RGMII only device) ?

Best Regards,

Machida