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DS90CR288AMTD Clock Functionality Question

Ethan Held22
Prodigy 680 points

Hi All, 

I have a question regarding the functionality of the DS90CR288AMTD related to the clock functionality.  The issue shows up more frequently at an elevated temperature (53C).  The IC is powered, the input clock is 32MHz, and the data lines are also connected.  The Power Down signal is asserted and at some point of time I de-assert the Power Down.

It appears that from time to time I do not see the Clock on the output of the SERDES. I would wait for 1.5s and assert the Power Down for a longer time (60s) and de-assert it again. The SERDES would generate the clock most of the time but in few instances this cycle has to be repeated one more time.  

Have you come across this before, and if so I'd like to understand the root cause of the issue and potentially if we can screen devices that exhibit this behavior.  Thanks in advance for any insight you can provide!

Thanks,

Ethan

  • 0
    TI__Mastermind 29655 points
    Hi Ethan,

    Are you working with another FAE regarding this question? This looks similar to something that I have already been supporting with another FAE via direct e-mail.

    To me, it looks like the power-up sequence issue. I suspect filtering on the power-down pin may be the cause of this, since this issue only happens to a subset of their devices after a significant time with the power-down asserted (meaning the chip is not being toggled on and off), and it seems like repeating the step 1 time after does the trick.

    For filtering, we usually use an RC low-pass filter, such as a 10k series resistance, followed by a 22 uF cap to GND to slow down the edge rate of the PDB signal and rule out the risk of unintended transients at the PDB assertion from tripping the ESD structure.

    Regards,

    Michael