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SN65DSI84 Clock Out Skew and Candence EVM Schematic and Layout

Other Parts Discussed in Thread: SN65DSI84

Hi,

What's the skew of A_CLK and B_CLK of SN65DSI84? And Can we provide the cadence or other format EVM schematic and layout? Thank you very much!

  • Is there any plan to release the Q100 grade SN65DSI84 products? If this is confidential, would you please send me an email at wayne.liu@ti.com? Thanks.
  • Hello Wayne,

    Theoretically, the CLK distribution should be nearly identical between two LVDS interfaces since both LVDS CLKS are generated from one CLK source so they are the same between two as the datasheet says. The skew is possible due to other mismatches but should not be greater than 10ps.

    I will send the files via email.

    Regards