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TSB81BA3E link interface receive data format in 1394b mode

Sung Lim
Prodigy 110 points
Other Parts Discussed in Thread: TSB81BA3E

I am using TSB81BA3E 1394 phy in 1394b mode (BMODE=1), where the PCLK output is always 98.304MHz.  The link controller is custom FPGA logic.  What is the receive data format on the D0-D7 bus, for each speed (S100,S200, etc.) ?   Is there a reference document that describes the format?

It appears that for S100 (only source I currently have), one data byte is transferred every 8 clocks (98.304Mbits/sec), which implies that at S200, it would be 1 byte per 4 clocks, etc.  However, S400B(491.52Mbits/sec) and S800(983.04 Mbits/sec) do not fit in 1 byte per N clock pattern.  S400b will require 5 bits per clock, and S800 in particular will require 10 bits per 1 PCLK, although the bus is only 8 bits.

  • 0
    Prodigy 110 points
    This is an update to the original question regarding TSB81BA3E receive in 1394b mode.
    I realized that 10b/8b encoding is used for S400b and S800 speeds, which means the link data rates will be 1 byte per 2 clocks for S400b and 1 byte per 1 clock for S800. So can one assume the following receive data format in 1394b mode?
    S100 : 1 byte per 8 clocks
    S200 : 1 byte per 4 clocks
    S400, S400b : 1 byte per 2 clocks
    S800 : 1 byte per 1 clock
  • 0 in reply to Sung Lim
    TI__Guru* 76130 points
    Hello,
    That is correct, for more information look at the Section 17.3 of the 1394-2008 Specification.
    Regards