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IEEE1588 PTP Demo

Guru 15510 points
Other Parts Discussed in Thread: DP83640

Hi,

I have a question about Ether PHY DP83640 IEEE1588 demo which are introduced
at following application report.
www.ti.com/.../snla098a.pdf

The question is about the demo written in page.3 "4 Software Reported Synchronization Test Results".
I want to know how the clock offset are calculated and show graphically with one PC.
Does PC get the value of counter from each board at same timing?

best regards,
g.f.

  • Hi g.f.

    The 1588 PTP stack is running on the PC. The stack uses the messages from the MAC layer to synchronize clocks kept on the PC. The 1588 PTP stack on the PC reports on the accuracy of the clocks kept in the stack. The PC is not taking the value of the counters from the boards, then comparing it. This would introduce an error caused by the USB access.

    From the app report, section 3:
    "Software testing relies on the results reported by the PTP stack to show the quality of the time
    synchronization. This means that the software results are subject to the same limitations as the PTP
    algorithm itself. The primary limitation of the PTP algorithm is that it cannot correct for differences in the
    length of the transmit path and the receive path. Another consideration when analyzing software results is
    that the reported error is always taken just before the time synchronization. Since the process is reporting
    an error that is essentially due to the drift between two clocks, the software error represents a worst case
    picture of the average time synchronization."

    Best Regards,
  • Hi Rob,

    Thank you for the reply and I'm sorry for the delay.
    I understood.

    best regards,
    g.f.