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Hi,
I have a question about Ether PHY DP83640 IEEE1588 demo which are introduced
at following application report.
www.ti.com/.../snla098a.pdf
The question is about the demo written in page.3 "4 Software Reported Synchronization Test Results".
I want to know how the clock offset are calculated and show graphically with one PC.
Does PC get the value of counter from each board at same timing?
best regards,
g.f.