Hi all,
I support a kernel driver for a PCI based DSP board in an embedded Win7 system.
The embedded PC in the past has always supported a native PCI bus. I measured interrupt latency on the order of 10-20 uS on our PCI based PC's, with occasional outliers.
We now have a new embedded PC that has PCIe, and we have added a AIO2001 PCIe to PIC bridge to support out PCI hardware.
It seems pretty transparent, except for our interrupt latency, which has jumped to 50-150 uS.
I measure the interrupt latency by writing a hardware line from the DSP board, which adds overhead, but not too much (~1 uS).
I do a second write to the hardware from the host code, which add a little more overhead, but it seems on the order of < 5 uS.
I understand that the bridge will convert a wired PCI interrupt to a message based interrupt. But I can't find any information on how fast this process should be. 50 uS seems way too long!
I am trying to decide if this is just the way it is, or is there something I can do to improve things.
