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TLK10232 HS errors

Erik Zanen
Prodigy 50 points
Other Parts Discussed in Thread: TLK10232

Dear all,


I am using the TLK10232 with SFP+ module on the HS side and 4x XAUI RX and 4x XAUI TX lane on the LS side(to a FPGA). Problem is that some of our boards give HS errors(no errors on LS side). Most of the boards give no errors, some give 1 or 2 errors per second and few boards give >100~200 errors per second. Boards that never give HS errors are always without HS errors(also after restarting etc).

On boards with HS errors the problems seem to come and go with resetting either the external 10G network switch and/or resetting our TLK10232(receiver disable than enable). We implemented the HS part exactly as the TI TLK10232 EVM board. We implemented initialization of the SERDES the same as in comments in the: e2e.ti.com/.../454808

I investigated and found a possible miss-match between the RX output of the SFP+(FCI TRX10GVP2010C2) module(300mV~850mV) and the input of the TLK10232(50mV~600mV). I also checked other brands(Avago e.a) but they have the same output amplitude. Can this be the problem?

Second question. How much does the backside of the SFP+ cage that stands perpendicular to HS traces to the SFP+ connector have (bad) influence on SI?

We are using HF PCB material and traces from TLK10232 to SFP+ are quite short(about 13mm total). Can this give any problems?

Thank you in advance,

Erik

  • 0
    TI__Genius 16150 points
    Hi Erik,

    This device is intended to backplane applications (10GBASE-KR), although is capable to interface with optical modules through 10GBASE-R. When this device is interfacing with SFP+ optical modules, the user needs to disable Link Training and Auto-negotiation (Clause 73). As you know every system is different, hence, you will need to adjust some parameters such as HS_SERDES_CONTROL_2 & HS_SERDES_CONTROL_3 to optimize the link (ENTRACK, SWING, EQPRE, etc.) according to length of traces, AC losses, among other factors that depends of the conditions of the system.

    I hope this helps.

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • 0 in reply to Luis Omar Moran
    Prodigy 50 points

    Hi Luis,


    Thanks for the fast answer. We already do all thinks that you mention. We also played a lot with these settings. Seems that when we connect two of our boards directly to each other via these SFP+ modules, we do not have any problems at all. Only if we connect to a switch we have these problems.


    Can you say something about the questions that I asked in my previous post?

    Thank you and regards,

    Erik

  • 0 in reply to Erik Zanen
    TI__Genius 16150 points

    Hi Erik,

    The TLK10232 is compliant with the SFF-8431 / Electrical standard, where to satisfy the requirements the nominal differential signal levels are ~500 mVp-p with edge speed control to reduce EMI. So, it shouldn't be an issue.

    Regarding the SI issues for the traces, the SFP/SFP+ module connectors are wider and hence have characteristic impedance that is lower than the regular high-speed PBC traces. If the pads are more than 2 times wider than the PCB traces, the pad's impedance needs to be increased to minimize impedance discontinuities. The easy way of increasing the pad's impedance is to cut out the reference plane immediately under those pads so as to have the pads refer to reference plane on lower layers while maintaining 100 Ohms differential characteristic impedance:

    On the other hand, you mentioned most of the boards don't have errors in the HS side (1 or 2 errors per second) in this case you could enable the FEC function (Forward Error correction) that is capable to correct a burst errors up to 11 bits. To use this function enable KR_FEC_CONTROL 0x01.000AB bit[0].

    In the case of the boards that you are having a lot of errors in the HS side:

    1. I am assuming that you have the same design for all boards right?

    2. When you initialize the device, how long is the reset time if you are performing the reset process through the RESET_N pin since it should be asserted for at least 10us.

    3. Could you send me the dumped register list when the errors appear in the HS side and also the dumped registers for the boards that don't have any issues? I would like to check in detail your configuration to discard any configuration issue.

    Best Regards,

    Luis Omar Moran

    High Speed Interface

    SWAT Team