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question about TLK10232 Loopback

Other Parts Discussed in Thread: TLK10232, TLK10034

Hi team,

         would you please help with below two questions about TLK10232 from my customer Moore? thanks.

1.       Loop back

Does TLK10232 have a LS loop back mode? My FPGA send 4 lanes of PRBS code to LS port of TLK10232. And I want TLK10232 just send back what it received.

         What DEEP REMOTE LPBK mode and SHALLOW LOCAL LPBK mean? Where are no more explanations on those in datasheet.

 

2.       Verify PRBS-7

I programed my FPGA to send PRBS-7 to 4 lanes of LS port of TLK10232.

The address 0x1E.15 is read out 0x8144, when address 0x1E.0C is set to 0x0370, 0x1370, 0x2370 and 0x3370, which means all 4 LS channel lanes sync status has been set.

And I set address 0x1E.0B to 0x0DD0, which means TLK10232 verifies PRBS-7 pattern on LS input and sends PRBS-7 pattern on LS output.

However, address 0x1E.11~0x1E.14 are read out many times and the value is always 0xFFFF. Does this mean that TLK10232 can’t receive FPGA normally?

What else I can do to figure the problem?


Kevin

  • Hi Kevin,

    1. The Deep Local Loopback accepts data on the low speed side SERDES, then data traverses the entire transmit data path, is returned through the entire receive data path and sent out through the low speed side transmit SERDES pins (OUT*P/N). The high speed side outputs on the HSTX*P/N pins are available for monitoring. The high speed side inputs on the HSRX*P/N should be electrically idle (floating):

    To enable this loopback mode, you must enable 0x1E.000B bit[1].

    For REMOTE LOOPBACK AND SHALLOW LOOPBACK modes please take a look into TLK10034 datasheet (Section  5.3.1.17), there are the description of these modes.

    2. It seems you are enabling the PRBS generator of the TLK10232 when you enable the bit [7] of 0x1E.000B. Please try setting 0x0D50 for this register to enable the PRBS verifier without the internal PRBS generator.

    I hope this helps.

    Best Regards,

    Luis Omar Moran

    High Speed Interface

    SWAT Team

  • hi Team,

    I use TLK10232 to verify my 10G data path is ok or not, so I connect HSTXAP/N with HSRXAP/N with PRBS7 pattern (follow tlk10232_BringupProcedures_v2.pdf, "10G in 4:1 or 2:1 mode, Link Training, with 122.88 MHz Refclk , Data Rate =
    9.8304Gbps" ), and it works because PRBS check correct. Now my question is if I conenct HSTXBP/N with HSRXAP/N on Hardware, that means I use Channel-A as PRBS7 source, and use Channel-B to verify, can it still work?

    Thanks!
    Simon
  • Hi Simon,

    If you want to connect HSTXBP/N ==> HSRXAP/N, you should use the channel B to generate valid data (source) and channel A to verify the pattern. The PRBS Generator and Verifier are located in the High Speed Side SERDES for each channel.

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • hi Luis,

    Thanks for your quick reply!

    I connected  HSTXAP ==> HSRXBP, HSTXAP ==> HSRXBP, on my test board. And I use following steps but CH-B prbs7 check fail.
    As I said before, I can generate and verify prbs7 successfully on Channel-A or Channel-B separated, following MDIO protocol Clause 45 timing.
    Take Channel-A case as an example, using PA[0]=0 when generating prbs, and using PA[0]=0 when check prbs.
    So when I do HSTXA ==> HSRXB, I use PA[0]=0 when generating, and using PA[0]=1 when check prbs in my MDIO timing set.
    //hardware control, power up both channel
    1. ST input pin is Low
    2. MODE_SEL input pin is High
    3. PRBSEN input pin is Low
    4. PDTRXA_N/PDTRXB_N input pin is High
    //software control, CH-A generate prbs, and CH-B to check
    1. WriteReg(0x1e, 0x80,0x21, 0x00,0x1f)         //write 0x001f to (0x1e, 0x8021)     // Reserved Register settings
    2. PRTAD0 => tie low on board
    3. WriteReg(0x1e, 0x0,0xb, 0x3d,0x10)           //2^7-1 PRBS Pattern HS, MDIO protocal timing PA[4:0]=00000
    4. PRTAD0 => tie high on board
    5. ReadRegCompare(0x1e, 0x0,0x10)             // check prbs, MDIO protocal timing PA[4:0]=00001
    My question is :
    1, Is there any mistake on my setting above, or as you know how to do it?
    2, if I use two TLK10232 chips to do TLK0_HSTXA ==> TLK1_HSRXA, does it still work on prbs7 check. Thanks!
    Simon
  • Hello Simon,

    Please try this quick sequence:

    ST ==> LOW
    MODE_SEL ==> LOW
    PRBSEN==> LOW
    REFCLK_SEL==> LOW


    Write 0x8610 to 0x1E.0000 //Reset the device
    Write 0x0E10 to 0x1E.0000//Global Write Both Channels
    Write 0x2000 to 0x07.0000 //Disable Autonegotiation
    Write 0x0000 to 0x01.0096 // Disable Link Training

    PRBSEN==>HIGH //Enable PRBS and Verifier in both channels
    Check PRBS_PASS pin

    With this procedure the device will be forced into 10GBASE-KR mode, disabling Autonegotiation and Link Training Features (Clause 73 Backplane), then the PRBS generator and verifiers are enabled through pin control and you can monitor thru PRBS_PASS pin if there are errors in the pattern.

    I hope this helps. Please let me know your results.

    Best Regards,
    Luis
  • By the way, this is an useful app note for BER Test of TLK10232/034. Please take a look:

    www.ti.com/.../slla351.pdf

    Thanks,
    Luis

  • hi Luis,
    I try the process as you mentioned, and it seems PRBS_PASS pin is always low (PRBS has error). I also do ReadRegCompare(0x1e, 0x0,0x10) and it is fail also.
    One question, I using TLK10232 to try run,but there is no REFCLK_SEL pin on this chip, so does is matter if I using default setting about REFCLK, with 122.88M external oscillator. 
    Maybe it is hardware issue because I using jumper wire on PCB board, so the performance can't be guaranteed. I will try again and will update to you if any impovement. Thanks!
    Best Regards,
    Simon
  • hi Luis,
    On test board, I connect HSRXA <=>HSTXB, HSTXA &HSRXB is floating.
    1,
     ST ==> LOW
     MODE_SEL ==> LOW (1G-KX mode?)
     PRBSEN==> LOW
    2, 
     Write 0x8610 to 0x1E.0000 //Reset the device
     Write 0x0E10 to 0x1E.0000//Global Write Both Channels
     Write 0x2000 to 0x07.0000 //Disable Autonegotiation
     Write 0x0000 to 0x01.0096 // Disable Link Training
    3, Enable PRBS
     PRBSEN==>HIGH //Enable PRBS and Verifier in both channels
    4, CHA check 
    ReadRegCompare(0x1e, 0x0,0x10)   //Read 0x1e,0x0100 to clear, CHA: PA[0]=0
    ReadRegCompare(0x1e, 0x0,0x10)   // check prbs, MDIO protocal timing PA[4:0]=00000
    CHA pass, because of register always =0.
    5, CHB check
    ReadRegCompare(0x1e, 0x0,0x10)   //Read 0x1e,0x0100 to clear, CHB: PA[0]=1
    ReadRegCompare(0x1e, 0x0,0x10)   // check prbs, MDIO protocal timing PA[4:0]=00001
    CHB fail, because of register always not =0.
    Here PRBS_PASS always low, My understanding is HSRXB has no data receive, and PRBS_PASS indicate both channels performance. So it can't be indicator for ONE channel (HSRXA <=>HSTXB)  pass or fail .
    It seems we verify the CH-A and CH-B data path, but the data signal generated is 1G prbs not 10G, I want to try 10G.
    So my question is does it possible to running 10G data on the this path, with some register setting?
    Or Could I using two TLK10232s, Chip 1 generate 10G prbs and the other to receive 10G prbs, like TLK_0_HSRXA <=>TLK_1_HSTXA or TLK_0_HSRXA <=>TLK_1_HSTXB?
    Thanks!
    Best regards
    Simon
  • Hi Simon,

    Sorry for the delayed response. Regarding the PRBSPASS, this pin depends of the PA[0], for channel A or B, since we are using both channels, in this case is not useful. So, you will need to force the device in 10GBASE-KR and use the PRBS31, and please try this procedure:

    • Device Pin Settings
    o Ensure ST input pin is Low
    o Ensure MODE_SEL input pin is Low
    o Ensure PRBSEN input pin is Low
    o Ensure REFCLK_SEL input pin is Low
    • Reset Device
    o Issue a hard or soft reset (RESET_N asserted for at least 10 us -or- Write 1’b1 to 30.0.15)
    Write 1'b1 to 30.0.11 GLOBAL_WRITE after device RESET.
    • REFCLK input frequency and selection
    o If using 156.25 MHz – Write 1’b0 to 30.29.12 (default)
    o If using 312.5 MHz – Write 1’b1 to 30.29.12
    o If REFCLK_0_P/N used – Write 1’b0 to 30.1.1 (default)
    o If REFCLK_1_P/N used – Write 1’b1 to 30.1.1
    • Default HS Tx settings loading and LT controls
    o Write 16’h2000 to 7.0
    o Write 16’h0000 to 30.150
    o Write 16’h0008 to 30.14
    o Write 16’h024D to 30.36864
    o Write 16’h0004 to 30.33025
    o Write 16’h0004 to 30.33024
    o Write 16’h0000 to 30.33024
    o Write 16’h0200 to 30.36865
    o Write 16’h3000 to 7.0
    o Write 16’h0002 to 30.150
    o Write 16’h1C00 to 30.36869
    • HS Serdes settings
    o Write to 30.3, 30.4 (Refer to “tlk10232 Link Training Optimization Guide” for recommended values)
    • Issue AN_RESTART
    o Write 1’b1 to 7.0.9 AN_RESTART
    • Wait for 1000ms
    Device provisioning is complete at this point.

    Enable KR HS test pattern generation
    o Vendor Specific Test Patterns
    231 – 1 PRBS / 223 – 1 PRBS / 27 – 1 PRBS – Write 1’b1 to 30.11.13
    o KR Standard Test Patterns
    231 – 1 PRBS pattern – enabled during test pattern select
    Pseudo Random – Write 1’b1 to 3.42.3
    Square Wave – Write 1’b1 to 3.42.3
    • Enable KR HS test pattern verification
    o Vendor Specific Test Patterns
    231 – 1 PRBS / 223 – 1 PRBS / 27 – 1 PRBS – Write 1’b1 to 30.11.12
    o KR Standard Test Patterns
    231 – 1 PRBS – Write 1’b1 to 3.42.5 or Write 1’b1 to 30.11.12
    Pseudo Random – Write 1’b1 to 3.42.2
    Square Wave – Verification not supported
    Clear Error Counters
    o Vendor Specific Test Patterns
    231 – 1 PRBS / 223 – 1 PRBS / 27 – 1 PRBS – Read 30.16 HS_ERROR_COUNTER to clear
    o KR Standard Test Patterns
    231 – 1 PRBS / Pseudo Random – Read 3.43 PCS_TP_ERR_COUNT to clear
    Square Wave – Verification not supported
    • Check Error Counters
    o Vendor Specific Test Patterns
    231 – 1 PRBS / 223 – 1 PRBS / 27 – 1 PRBS – Read Verify 30.16 HS_ERROR_COUNTER –
    (16’h0000)
    o KR Standard Test Patterns
    231 – 1 PRBS / Pseudo Random – Read Verify 3.43 PCS_TP_ERR_COUNT – (16’h0000)
    Square Wave – Verification not supported

    I hope this helps.
    Best Regards,
    Luis