Hi Team,
The customer is using TSB81BA3E,TSB12LV01B and FPGA with the hardware structure of AS5643 protocol for their design.
They found it cannot send the data without cycle start packet, so they have several issues as follows:
Q1: How to send asynchronous streams packets when TSB12LV01B neither transmiting cycle start packet nor receiving cycle start packet?
Q2: Is there any mistake to achieve the AS5643 protocol by using TSB81BA3E and TSB12LV01B? Do you have any recommend advices for achieving the AS5643 protocol?
Q3: Can you send me the full data sheet of TSB12LV01B ? E-mail: mickey-zhang@ti.com
Thanks,
Best Regards,
