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[SN65DSI85] how to set SYNC_DELAY_LOW/HIGH bit

Ryuuichi machida
Guru 12715 points

Hi,

There is following description in datasheet.

However, there is no description about how to set these bitfield's value.

So, could you please tell me calculation formula about how user decide these bitfield's value ? 

Best Regards,

Machida

  • 0
    TI__Mastermind 18655 points
    Hello Machida,

    The DSI input timing parameters MUST match the calculated value by the DSI Tuner tool(calculated based upon the DSI configuration and panel requirements). The DSI85 does not realign the timing. The line time presented in the DSI input should remain the same at the LVDS output(per the panel requirement). The mismatch of the timing may result in internal buffer underflow/overflow which typically flag the errors you are reporting(SOT and LLP error).

    Regards
  • 0 in reply to Joel Jimenez0
    Guru 12715 points

    Hello Joel-san,

    Thank you for your reply.

    The DSI input timing parameters MUST match the calculated value by the DSI Tuner tool(calculated based upon the DSI configuration and panel requirements).

    I understood that we need to use DSI Tuner tool to understand values of SYNC_DELAY_LOW/HIGH bits.

    However, I'm not sure why TI does NOT disclose calculating formula on datasheet.

    Is the reason that this is TI internal information ?

    Best Regards,

    Machida