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LVDS deserializer for interfacing AFE5809 with PRU-ICSS?

Dehuan Xin94
Intellectual 520 points
Other Parts Discussed in Thread: AFE5809, AM5728, DS90CF388, DS32EL0421, DS32EL0124

Hi, everyone,

I'm thinking about interfacing AFE5809 with PRU-ICSS on TI AM5728 application processor.

Theoretically if 4-channel LVDS output from AFE5809 can be deserialized to 4 channels of 16 bit parallel bus, it should be trivial to use PRU-ICSS to detect the sync word and stream data into memory (there are 4 PRU-ICSSes in AM5728 and each has a 21-bit parallel input).

However I searched over TI's catalog but I didn't find a particular deserializer for this task. Specifically the desired deserializer should have 16x deserialization, DDR DCLK input (DDR serial bit clock) and FCLK input (SDR clock for each 16-bit word). 

I'm aware that this can be easily implemented using FPGA, but I'm still interested in a ASIC solution to see if there's any cost/power/performance/size advantages.

Thank you.

Dehuan

  • 0
    TI__Guru* 93570 points
    Hi Dehuan,

    Have you looked at DS90CF388? Perhaps this may meet your requirements. I am thinking you can operate DS90CF388 in single pixel mode for this application.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Intellectual 520 points
    Hi, Nasser,

    I checked the datasheet and it seems like a (6+1):1 deserializer (6 bit data + 1 bit DC balancing).
    From what I see, the protocol of AFE5809 is most similar to FlatLink I, but non of the FlatLink I products provides plain 16:1 deserialization.

    Dehuan
  • 0 in reply to Dehuan Xin94
    TI__Mastermind 29655 points
    Hi Dehuan,

    I looked at the AFE5809 output format, and it seems like the DS90CF388 will not work here. Our Channel Link/FPD-Link (Flat-Link) I devices assume that the incoming data uses OpenLDI format, which means that the incoming LVDS data is serialized with 7-bits of data within one LVDS clock cycle. We do not interact with a format that has 16 serialized bits, moreover one that supports DDR clocking.

    The closest I can think of is that we do have some general purpose SerDes devices like the DS92LV1023E and DS92LV1224, which is a 10-bit SerDes, and this operates with SDR, not DDR. The only DDR-type device we have is the DS32EL0421 and DS32EL0124, serializes up to 5 lanes of 4-LVDS bits per clock cycle onto a single pair.

    Unfortunately, I think you may be looking at an ASIC/FPGA solution for your application need.

    Regards,

    Michael