Cannot disable DS90UB947 streaming its internal clock when no PCLK is present

Ondrej Hnilicka

Hello,

I have a problem with DS90UB947 serializer. When I stop its input PCLK clock (I cut its input signal), it still streams out some FPD Link 3 signal. The signal consists of clock of the last frequency and no data. It seems PLL has been locked to a last frequency and serializer streams out despite of lack of input (OpenLDI) PCLK signal. I have to perform serializer reset to stop streaming and restore PCLK signal to start it again. I disabled "PCLK Auto" bit in "General Configuration" register (Disable auto-switch) but with no effect.

The serializer also signalizes "PCLK Detect" bit = 1 in "General Status" register despite of PCLK clock is disconnected. I see no PCLK on oscilloscope, but this bit is still 1. It sets 1 after first valid PCLK and never goes 0 when PCLK disconnects. Is this correct behavior?

I need to stop the steaming of internal clock when PCLK is off. My device causes problems down the FPD Link. Do you know a more elegant solution than reseting the serializer every time the input PCLK stops?

Thank you.

Ondra

over 9 years ago

0 Mirko Paggi over 8 years ago

Prodigy 10 points

Hi Ondrej,

did you solve the issue?

We have an issue very similar to the yours.
We drive the serializer DS90UB947 with a constant pixel clock at 33MHz.
In normal cases, at receiver side (we use a DS90UB926 as deserializer) we measure the same frequency on pixel clock pin.
When the issue occurs, at receiver side we measure a frequency of pixel clock equal to ~32.5MHz.
In this condition all the data (R/G/B, VSYNC, HSYNC) are wrong and on video we see a flickering effect.

By reading the internal registers of the serializer, all seem to work properly: PLL is locked and all other status bits are ok.
To restore the full functionality a reset of the serializer must be executed.

Thanks in advance,

Mirko

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Cannot disable DS90UB947 streaming its internal clock when no PCLK is present