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TLK10034: 10GBASE-KR auto-negotiation based on the Low Speed interface link speed

Zach Candee
Prodigy 60 points

Other Parts Discussed in Thread: TLK10034

I have a board which uses the TLK10034 to convert four 10GBASE-KR interfaces to XAUI which is then routed to the backplane.    I've noticed that if a 1G link is presented on the highspeed side the lowspeed side will train the XAUI down to 1GBASE-KX.  However the opposite is not true, if a 1G link is presented on the XAUI side neither side will train at all unless I disable 10GBASE-KR advertising and enable 1GBASE-KX advertising (bits 7.17.7 and 7.17.5).  

Is there a way to allow the XAUI (low speed) interface to dictate what speeds are advertised on the high speed side?

I have the TLK10034 strapped in 10G-KR/1G-KX mode and changed the following registers to optimize the 10G link:

 7.17  0x00A0
30.2   0x831D
30.3   0xA848
30.4   0x7900

  • 0
    TI__Genius 16150 points
    Hi Zach,

    What value do you have in the register 0x07.0000 (AN_CONTROL) & 0x07.0001 (AN_STATUS)?

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • 0 in reply to Luis Omar Moran
    Prodigy 60 points
    Hello Luis,

    AN Control is always 0x3000 and AN Status alternates between 0x00ED and 0x0089.

    Thanks,
    Zach
  • 0 in reply to Luis Omar Moran
    Prodigy 60 points

    Hello Luis,

    I'm not sure if you got my last reply but I was able to poll the status registers and capture those registers.  7.0000 is always 0x3000 and 7.0001 toggled between 0xAD, 0xED, 0x88 and 0x89.  Below is a snapshot of the registers I am polling:

    Link Status registers...
  Channel 0...
    1e.000f  Channel Status 1...        0x1C03
    1e.0010  HS Error Count...          0x0000
    1e.0011  LS LN0 Error Count...      0xFFFF
    1e.0012  LS LN1 Error Count...      0xFFFF
    1e.0013  LS LN2 Error Count...      0xFFFF
    1e.0014  LS LN3 Error Count...      0xFFFF
    1e.0015  LS LN0 Status...           0x0809
    1e.0015  LS LN1 Status...           0x0C08
    1e.0015  LS LN2 Status...           0x0C08
    1e.0015  LS LN3 Status...           0x0C09
     1.0001  PMA Status 1...            0x0086
     3.0001  PCS Status 1...            0x0086
     7.0000  AN Control...              0x3000
     7.0001  AN Status...               0x00AD

HS Final registers...
  Channel 0...
    1e.8031  HS Serdes Status 1...      0x2000
    1e.8032  HS Serdes Status 2...      0x080A
    1e.8033  HS Serdes Status 3...      0x037B

    Link Status registers...
  Channel 0...
    1e.000f  Channel Status 1...        0x1803
    1e.0010  HS Error Count...          0xFFFD
    1e.0011  LS LN0 Error Count...      0xFFFD
    1e.0012  LS LN1 Error Count...      0xFFFD
    1e.0013  LS LN2 Error Count...      0xFFFD
    1e.0014  LS LN3 Error Count...      0xFFFD
    1e.0015  LS LN0 Status...           0x0801
    1e.0015  LS LN1 Status...           0x0C00
    1e.0015  LS LN2 Status...           0x0C00
    1e.0015  LS LN3 Status...           0x0C01
     1.0001  PMA Status 1...            0x0082
     3.0001  PCS Status 1...            0x0082
     7.0000  AN Control...              0x3000
     7.0001  AN Status...               0x0089

HS Final registers...
  Channel 0...
    1e.8031  HS Serdes Status 1...      0x2000
    1e.8032  HS Serdes Status 2...      0x080A
    1e.8033  HS Serdes Status 3...      0x037B

  • 0 in reply to Zach Candee
    TI__Genius 16150 points

    Hi Zach,

    Could you try disabling the Link Training? Write 0x0000 to 0x01.00096. Normally, Auto-Negotiation occurs first and helps to synchronize what time both ends of the link go into link training (since they finish auto-negotiation together).

    Please try disabling this feature, and let me know the result. I hope this helps.

    Regards,

    Luis

  • 0 in reply to Luis Omar Moran
    Prodigy 60 points

    Luis,

    Thank you for the suggestion, I was able to try disabling the link training which lead to the link partners repeatedly auto-negotiating.  Below is an excerpt including all of the configuration I've done and several status register reads showing AN toggling.

    Configure HS TX and LT (per TLK10232 Bringup v2)...
  1e.0000  Enable global writes...    0x0820
   7.0000  Disable AN...              0x2000
   1.0096  Disable KR Training...     0x0000
  1e.000e  Restart datapath...        0x0000
   7.0011  Enable 1GBASE-KX...        0x00A0
   7.0000  Enable AN...               0x3000

Configure HS Serdes...
  1e.0002  Enable high loop BW...     0x831D
  1e.0003  1020mV TX swing...         0xA848
  1e.0004  No preEQ; 8vote 2x CDR...  0x7900

Restart Auto Negotiation...
   7.0000  Restart AN...              0x3000
  Done.

Waiting for PLL lock... Acquired. (1A03)

Waiting for AN. Complete. (00ED)

Waiting for link training........................
.................................................
.................................................
.................................................
.............................. Failed. (0000)

Clear sticky registers................Done.

Link Status registers...
  Channel 0...
    1e.000f  Channel Status 1...        0x1803
    1e.0010  HS Error Count...          0x0000
    1e.0011  LS LN0 Error Count...      0xFFFF
    1e.0012  LS LN1 Error Count...      0xFFFF
    1e.0013  LS LN2 Error Count...      0xFFFF
    1e.0014  LS LN3 Error Count...      0xFFFF
    1e.0015  LS LN0 Status...           0x0808
    1e.0015  LS LN1 Status...           0x0C08
    1e.0015  LS LN2 Status...           0x0C08
    1e.0015  LS LN3 Status...           0x0C08
     1.0001  PMA Status 1...            0x0082
     3.0001  PCS Status 1...            0x0082
     7.0000  AN Control...              0x3000
     7.0001  AN Status...               0x00AD
     7.0001  AN Status...               0x0088
     7.0001  AN Status...               0x0089
     7.0001  AN Status...               0x00ED
     7.0001  AN Status...               0x00AD
     7.0001  AN Status...               0x0088
     7.0001  AN Status...               0x00CD
     7.0001  AN Status...               0x008D
     7.0001  AN Status...               0x00AD
     7.0001  AN Status...               0x0088
     7.0001  AN Status...               0x00ED

  • 0 in reply to Zach Candee
    TI__Genius 16150 points

    Hi Zach,

    To avoid issues with having link training start at independent times for each side of the link, the easiest solution is to disable the time-out counter that is used for link training.  The device has a 500-ms timer that is implemented in registers 0x01.9002 (MS 16 bits) and 0x01.9003 (LS 16 bits).  If you set both of these registers to 0x0000, the time-out counter is disabled.  Link training completion will still be signaled by the normal "link up" indicators in the PCS register space.

    Regards,

    Luis

  • 0 in reply to Luis Omar Moran
    Prodigy 60 points

    Hi Luis,

    I tried disabling the AN timeout but saw the same results with the AN Complete bit in the AN Status register toggling.  I also see the AN LP Ability bit (7.1.0) toggle when AN restarts.  Is it possible that the LP is forcing the link to renegotiate because both sides advertise 10GBASE-KR but the TLK10034 will only support 1000BASE-KX?  Is there a way to stop the TLK10034 from advertising 10GBASE-KR when the XAUI side is linked at 1G?

    Thanks,

    Zach

  • 0 in reply to Zach Candee
    TI__Genius 16150 points
    Hi Zach,

    Auto-Negotiation occurs only in the High Seed side. The Low Speed side will sends Idles at 3.125G until ready. If the HS side says 1G, then both switch to 1G and 3 of the 4 LS lanes (that are unused) turn off.
    So, if you are running 1G, you do not really have to use A-Neg, you can just set it to 1G (although it should work either way). In fact, during a-neg, if we see 1G traffic (HS side only), we'll stop a-neg and just switch to 1G immediately. You can also force the device into 10G (General Purpose Mode), but that's typically only doing for optical links.
    If it's supposed to be 10G, then it's probably running a-neg and link training, establishing link, then failing which causes a restart of the a-neg/LT process. The RX SERDES settings may need adjusting.

    Regards,
    Luis
  • 0 in reply to Luis Omar Moran
    Prodigy 60 points

    Luis,

    Thanks for the quick reply!  I understand that a-neg is only on the HS and that the LS side only uses 1 lane for 1G links.  I recognize that typically the HS side dictates the speed to the LS but I need a way to force the opposite: "If the LS side says 1G, then both switch to 1G." 

    My application connects the LS lanes across a backplane to an unknown link partner that may support either 10G or 1G while the HS always connects to my processor's 10GBASE-KR port.  Since the LS link speed is not predetermined and can be either 10G or 1G, I need a mechanism to force 10G or 1G A-Neg on the HS side after the LS link is established.    

    Thanks,

    Zach

  • 0 in reply to Zach Candee
    TI__Genius 16150 points

    Hi Zach,

    There's only one way to do this but it's not automatic. It requires their host to monitor status from our part and then change settings accordingly. There is no "set it and forget" mode of operation. But if that's doable, here's the plan

    //1) Disable ANEG. This will keep the device on the HS side busy as it is waiting on ANEG.//
    2) Read Lane 0 LS_STATUS_1 and check bit 8, LS_CH_SYNC_STATUS. (Have to read 2x since this is a LL bit).
    a) If status is 1, we're at 10G, so just enable/restart ANEG (write 0x3200 to 0x7.0x0000).
    b) If status is 0, we're *probably* at 1GKX. Change the AN_CAPABILITY bits (7.16.12:10) from 100 to 001 (i.e. write 0x0401 to 0x07.0x0010). Enable/restart ANEG. Now check LS_CH_SYNC_STATUS and it *should* be 1. If not the whole link is down so you have to try 10GKR again. Just set 7.16.12:10 back to 100 and restart ANEG. Check LS_CH_SYNC_STATUS, etc. Repeat until link is up.

    One thing you might be thinking, is that is when we're trying 1GKX, why not just set the device into 1GKX mode directly for this step (SW_PCS_SEL=0) instead of doing ANEG? Well that works, too. The reason in, their 10G-KR device on the HS side will see our 1GKX data and switch to 1GKX, even though we didn't do ANEG (at least it's supposed to, that's what our device does). So really either way works. If it's not 1GKX because the link is just dead and you want to try 10G-KR again, you either change SW_PCS_SEL and then enable/restart ANEG, or you change the AN_CAPABILITY bits back to 100 and restart ANEG.

    Is important to mention that really don't have to do step 1, as ANEG is going to be on at power up and will also negotiate to 10G-KR. So might as well just leave it alone until we figure out if it's right or not. Disabling it doesn't really do much other than change their 10G-KR part back to ANEG while it waits for us to return to ANEG. So quick summary is, just change the AN_ABILITY bits and restart ANEG to change the other mode.

    I hope this helps.

    Best Regards,

    Luis