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TLK105 maximum XI clock start delay time allowed from VDD power-up

F.N
Expert 8760 points

Hi team,

This customer can't input XI and VDD at the same time.

So, the customer wants to know the maximum XI clock start delay time allowed from VDD power-up.
Please let me know.

Best regards,
Fumio Nakano

  • 0
    TI__Mastermind 18425 points
    Hello Fumio,

    The device needs a stable clock when VDD is applied because the device performs POR, if a stable clock is not present then the PHY can be incorrectly initialized. If the clock is applied later, I would recommend applying an external reset pulse after the clock is stable. The reset pulse should be atleast 1us long.

    -Regards,
    Aniruddha