Other Parts Discussed in Thread: SN74LV595A, TPL0501-100
I am planning to use TPL0501-100 in a test instrument project. The system has today a few "clients" on a SPI bus with each device having their dedicated /CS line. So far all well, but I am running out of /CS lines. However, I have a 24 bit SPI-write-only register built of three SN74LV595A serial-in/parallel-out shift registers. I could maybe connect the TPL0501 in the "exit-end" of the last shift register (QH'), and share the same /CS line. That way, what I would be doing, would be lowering the /CS, writing the setting of TPL0501 followed by the data intended for that 24-bit shift register, and raising the /CS line again. In other words, the whole register + the digital potentiometer would be written as one 32 bits word, and by the time /CS goes high, the intended 8 bits should be in the receiving register of the TPL0501 chip.
The data sheet description of this device assumes that only 8 bits are sent for each SPI transaction. However, if the receive register is implemented the "easy way" as a shift register and a parallel buffer (roughly like for instance that SN74LV595A) the superfluous first 24 bits bits would be just flushed out without any consequences whatsoever, and the correct 8-bit value latched at the rising edge of the /CS.
I would like to know if anybody has either tested this or if there is somewhere documentation about behavior of TPL0501 in this situation?
