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DS90CR287 Clock quality issues

Dan Whitehead
Prodigy 90 points
Other Parts Discussed in Thread: DS90CR287, DS90C385A

I'm working with a DS90CR287 chip and I am seeing dropped clock cycles on the output clock (TXCLKOUT) when running at 20MHz, which is the minimum spec'd clock frequency. There is significantly more jitter on the output clock than I would have expected (~2ns) considering the input clock is incredibly clean. This seems to be causing problems with one of our frame grabbers. Is there anything that would be causing the poor output clock?

  • 0
    TI__Mastermind 29655 points
    Hi Dan,

    Is it possible for you to share your schematic as well as scope shots of the clock signal before and after the DS90CR287?

    There can be issues on the transmit input clock, with the below being the most likely possible reasons:
    1. There is noise on the PLL power supply. This can be improved by additional decoupling cap filtering.
    2. There is impedance discontinuities either in the interconnect media or termination resistor at the receiving end of the LVDS clock.

    What happens if you run at a higher clock rate? Do the issues disappear?

    If it is a question about margin on the low-end operating range for the input pixel clock, it may be worth looking at the DS90C385A as an alternative transmitter (min = 18.5 MHz).

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 90 points

    Hi Michael,


    I can't share the schematic on the forum but we do have the 0.001uF, 0.01uf, and 0.1uf capacitors on the LVDS and PLL power as specified by the datasheet. The test setup has the output of the DS90CR287 going through a 3 or 9 foot Camera Link cable and it is received on the other end by a DS90CR288. There is a 100Ohm resistor across each of the differential pairs at the receiving end.

    At high clock rates the jitter decreases, but the DS90CR288 we are receiving the signal with seems to amplify the jitter to unusable levels.

    Single-ended input clock @ 20MHz

    LVDS Output clock @ 20MHz

  • 0 in reply to Dan Whitehead
    TI__Mastermind 29655 points

    Hi Dan,

    I only recently realized that this thread has gone unanswered since your last post. I apologize for this! Has there been progress made with this issue?

    From the output of the LVDS clock, it seems reasonable, centered at 0-V differential and about 750-800 mVpp. The media length also should not be an issue, since 3 ft is a short distance. If this issue has not been solved, do you see an improvement if you try replacing the DS90CR288, or is it reproducible on every DS90CR288 IC? Same question for the DS90CR287. I am wondering if this may be an issue of one IC not having enough margin while another IC does.

    Thanks,

    Michael