Dear Team,
my customer has some questions to the power-up of the TUSB1210 device.
We are currently using the TI TUSB1210 USB transceiver chip as a USB PHY. We are using it in the ULPI (external) clock input mode where the FPGA provides the 60MHz input clock. I have a question about the power on sequence timing diagram shown in Figure 4-1 for the ULPI clock input mode.
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It shows the RESETB @ pin 27 rising at the same time as the 60MHz input clock. Is this a requirement or is it OK for the clock to rise before or after the RESETB?
2. Also does it really require the VDDIO & VDD18 voltage to start to rise BEFORE the VBAT and internally generated VDD33 have reached their final voltage or is it OK for VDDIO & VDD18 to just rise after VBAT & VDD33 have risen and is there a timing constraint they must meet?
3. Is there a need for VDDIO to start ramping before VBAT is fully ramped? If yes, what is the limit of the max voltage difference of VBAT and VDDIO?Thanks and best regards,
Joe
