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[ LMH1982 ] No lock indication of SD_LOCK

Kenichiro
Mastermind 9165 points
Other Parts Discussed in Thread: LMP7701

[ LMH1982 ] No lock indication of SD_LOCK

Hi,

Can you help to clarify the behavior which SD_LOCK does not indicate lock status as expected.
My customer has reported following information.

* SD_LOCK is NOT asserted.
* However It seems that the input reference and output clock are in-lock. (checked by oscilloscope.)
(It seems that device is not in FREE RUN mode.)

I have checked some points from customer circuit and register settings as below.
- LOCK_CTRL: max (0x01h = F8h)
- REF_VALID, HD_LOCK are asserted.
- Customer changes REF_DIV, FB_DIV and ICP1 based on input format.
- ICP1 setting is enough large compare with limitation (described in datasheet)
- no High-Z amp (ex LMP7701) is used in loop filter circuit.

I'm bit concerned that they don't have high-z amp, so the leakage current would prevent device to establish valid lock condition. So may be it's reasonable to check the behavior with slightly larger ICP1 value.

It's really appreciated, if you have any comments and/or ideas. 
Thank you for your support in advance.
Regards,
Ken


  • 0
    TI__Mastermind 32575 points

    I agree with your comment:

    I'm bit concerned that they don't have high-z amp, so the leakage current would prevent device to establish valid lock condition. So may be it's reasonable to check the behavior with slightly larger ICP1 value.

    This could cause enough phase offset for the lock detector to not indicate lock, when in fact the PLL is actually locked.

    Alan

  • 0 in reply to Alan O
    Mastermind 9165 points
    Alan,

    Do you have a recommended value or indication for which ICP1 value is required for xxx impedance?

    The VCXO on their board is model VG-4231CE from Epson with 5Mohm (min) input resistance.
    www5.epsondevice.com/.../vg4231ce.html

    It's greatly appreciated if you can share the ICP1 value for this VCXO.

    Thanks,
    Ken
  • 0 in reply to Kenichiro
    TI__Mastermind 32575 points
    It should be OK to maximize the ICP1 value to test if it helps reduce PLL PFD input phase offset due to leakage on the Vc node. This will increase the BW and DF slightly.

    Besides VCXO input impedance, another potential leakage path is leakage loop filter caps. Did they select loop filter caps with low leakage?