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DP83867 - GTX_CLK an input?

Brian Antheunisse
Expert 5305 points

I have a customer asking me the following question:

"I’m looking at the datasheet for a PHY (DP83867).  The pin function description shows GTX_CLK as an input, but shouldn’t it be an output from the PHY to the MAC? 

I’m new to this interface, but I would think the PHY would need to generate this clock since it depends on link speed, and the link speed is controlled in the PHY."

Regardless of that answer I noticed in the datasheet that the TX_CLK is not even required in speeds above 100 Mbps. 

Can you guys educate us on how that works? =)

Thanks,

Brian 

  • 0
    TI__Mastermind 23675 points
    Hi Brian,
    TX_CLK is an input for RGMII operation. RX_CLK is an output for RGMII operation. There are methods that allow for clock stretching to occur to prevent issues during speed changes.

    Just for reference, in MII mode, TX_CLK and RX_CLK are both outputs from the PHY.

    Kind regards,
    Ross
  • 0 in reply to Ross Pimentel
    TI__Expert 5305 points

    Ross,

    So if operating in RGMII mode, the MAC just needs to supply a 125MHz clock to the TX_CLK, and if there are any speed changes, the DP83867 just stretches the clock down to 25MHz or 2.5MHz if the speed changes lower than Gbps rates? But traditionally with older PHYs running in an MII mode, this is not the case and the PHY would need to supply both clocks?

    thanks,

    Brian

  • 0 in reply to Brian Antheunisse
    TI__Mastermind 23675 points
    Hi Brian,

    Sorry for not being clear and my miss typing above.

    RX_CLK is allowed to stretch for speed changes and also for transitioning from a free running clock to a data-synchronous clock that is locked to the data stream on the cable.

    The MAC is required to hold TX_CLK low until it has ensured that the PHY and MAC are both operating at the same speed.

    To inform the MAC about the speed, duplex and link status, PHYs will present an in-band status on the RX pins (please see page 30 in the DP83822 datasheet for information about in-band status). Additionally, the MAC can use register access through the SMI (serial management interface) to find the status of link, speed and duplex.

    For MII you do not run into this issue above because both clocks are supplied by the PHY.

    Kind regards,
    Ross