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DP83867IS with SGMII to MAC- Is it possible to get 125MHz single ended Recovered Clock ?

Mizanur Chowdhury
Genius 17270 points
Other Parts Discussed in Thread: DP83867IS

Hello Team,

One of our customer wants to replace a competitor part by using DP83867IS with SGMII support as this is the MAC interface they use. They claim the competitor device provides with a 125MHz recovered clock which is needed for clock synchronization. To my understanding SGMII uses differential pairs for data and clock , the clock being 625MHz always which is also mentioned in DP83867IS datasheet. In RGMII the device can give a 125MHz recovered clock. Is there a way that the customer gets a 125MHz single ended recovered clock needed for the synchronization in SGMII mode?

Thanks and regards,

Mizanur

Central Apps, EMEA

  • 0
    TI__Mastermind 19780 points
    Hi Mizanur,

    There is a way to generate 125MHz clock using the CLK_OUT pin of the DP83867IS. The 125MHz clock is the recovered clock from the Ethernet cable however and is not the same clock as the MAC interface.

    Please see the description of register 0x0170 for receive clocks that can be placed on the CLK_OUT pin.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    TI__Intellectual 1625 points

    Hello Rob,

    I know this is a closed post, but I was hoping if you could review the case below since it is very similar.

    I have a customer with a similar application request.

    " In my schematic I am designing (we haven’t gone to layout yet) I connected the SGMII_CO[p,n] pins of your device (DP83867IS) to the MGT REF CLK input (through DC Blocking caps) on my Xilinx FPGA. However, my firmware guys are telling me they are expecting a 125MHz clock input. Why is the part outputting a fixed 625MHz clock (that I can’t change) if the Xilinx FPGA MGT Quad is expecting 125MHz? "

    I also would believe it is because SGMII uses differential pairs for data and clock , the clock being 625MHz as mentioned above by MRC. Is there an app note for your above suggestion that the customer can use?

    Thank you for your time.

    Kishen

  • 0 in reply to Kishen Someshwar
    TI__Mastermind 19780 points
    Hi Kishen,

    SGMII_CO is a 625MHz, differential clock as you have stated. The requirement for a MAC to take in 125MHz single-ended reference to synchronize with SGMII (625MHz) is unusual. Semi-conductor manufacturers typically include CDR circuits to recover the 625MHz clock from the data, like the DP83867IS.

    We do not have an app note for interfacing with the Xilinx FPGA that requires 125MHz.

    You can use the CLK_OUT pin to generate 125MHz by setting register 0x0170 to output one of the channel TX clocks. These are always 125MHz.

    Best Regards,