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TUSB7320 External clock & Power Down

Shareef
Expert 1985 points
Other Parts Discussed in Thread: TUSB7320, TUSB7340

Hi,

I have two questions on TUSB7320 device, they are

1. In TUSB7320 device, 1.8V supply is being to clock the oscillator. Can the clock oscillator be enabled before the VDD33 and VDD11 supplies come up? Or it need to be enabled after VDD33 and VDD11 supplies have ramped up.

2. PERST# in my design is being controlled by a GPIO of PCIe host. During Power Down sequence, the PERST# signal will get asserted and the PCIE REFCLK clocks will get disabled simultaneously. Then after a few ms the VDD33 and VDD11 will be removed. Is this fine?

3. Does the TUSB7320 device require ac coupling and 100 ohms parallel termination to interface with a HCSL clock driver output?

Thanks,

Shareef

  • 0
    Expert 1985 points

    Hi,

    Can anyone from TI please respond on this?

    Regards,

    Shareef

  • 0 in reply to Shareef
    TI__Guru* 76130 points
    Hello,
    For 1) and 2):
    The power up/down sequences are required in order to assure the correct functionality of the device at any time, we can't guarantee the correct functionality if the specs are not met, that being said, it is very probably that you won't have issues with those scenarios.
    3) No, the clock lines must be DC coupled, the TUSB7340 does not incorporate internal terminations on the REFCLK lines.
    Regards