Hello everyone,
We are working on gigabit Ethernet implementation in zynq processor with following part number.
Gigabit Phy: TI DP83867ir-RGMII interface
Lwip driver: 141-v3.
Implementation and testing details:
1. All the TI phy signals were routed to MIO pins (Eth0), except reset and clock.
2. Both reset and clock were routed from PL to PHY section.
3.Verification was done across MDIO and MDC interfaces of PHY. As we are able to read the phy address(15) and detect mask(0xa231), we are not suspecting any issue with management interface.
4. More over link is getting established between PC and hardware. But "Ping" is not happening.
do we have to modify any parameter values in the xilinx PHY or MAC driver w.r.t TX and RX clock delays in the RGMIIDCTL?
or
does we are missing anything in the implementation procedure.
Requesting to give some suggestions for debugging process.
