I would like to use SN65LVDS17 as an LVPECL receiver with enable. During normal operation it may have its Vcc pin turned off. More specifically, the Vcc pin is connected to the (always on) 3.3V rail through a PFET, with the PFET being turned off.
The A and B input pins, in this situation, will still be driven by an (off-board) LVPECL clock (worst-case excursions: 1.475V-2.405V).
The SN65LVDS17 datasheet states that the A, B pins should stay between -0.5V and Vcc + 0.5V. Since "Vcc" when powered off will be at 0V, this range translates into -0.5V to +0.5V, which the LVPECL clock input will be exceeding on the positive side by quite a bit. I'm pretty sure, though, that the underlying reason is that the input protection diodes (represented on p.10 of the datasheet - see snippet below) must not be made to conduct significant currents. The only one at issue here is, I think, the upper diode, which clamps the input to the device's Vcc pin. Since this pin is effectively floating, when the PFET is off, little if any current should ever flow through this diode.
Alternatively, the Vcc pin could be tied to the on-board 3.3V rail through a Schottky diode (like 1N5819HW). The SN65LVDS17 operates down to Vcc=2.375, and the voltage drop through the diode should be less than 0.32V, ensuring that the device Vcc pin will be well within spec. When the 3.3V rail is off (0V) the diode should effectively float the device Vcc pin, like the PFET does in the above method. (The diode method doesn't, however, support operation from an on-board 2.5V rail, since the diode cathode would be below the device operating range.)
Assessments of both of these methods will be appreciated.
Thanks!
Noble Larson
Axsun Technologies
Billerica, MA