We are facing an issue with DP83848 Ethernet PHY while reading the PHY registers via MDC/MDIO interface after completion of data transfer in PHY loop back mode at 100Mbps(MII mode). Please check the below sequence: 1. Controller Initialization in 100Mbps mode. 2. PHY enablement via MDC/MDIO interface for 100Mbps and PHY loopback mode. 3. Initiating data-transfer and successful completion. 4. Reset the PHY by setting the BMCR's MSB. 5. Reading back BMCR but returning FFFF. Note: This sequence works fine in 10Mbps mode.
Response from TI - you done the test of BIST internal loopback with 100Mbps? Is it passed or not? During the BIST test, make sure the MII connections to the DP83848 are not being driven or pulled.If the MII inputs (e.g. TX_EN) are being driven or pulled during the test, it could cause a problem
Reply to TI -
Here are my test results. This sequence is passing and working even after data transfer operation. It means I am able to write and read back values from these register. But moment I try to reset the PHY by writing register 0x0 it is not working for me as already explained .
BIST Testing Steps;
Reset Phy ( Write value 0x8000 to register 0x0)
BIST start ( Write value 0x8121 to register 0x19)
Poll for BIST pass in register 0x19.
Also check register 0x1B for if any error count.
Further Response from TI -
1. Once you lose communication to the PHY how do you get it back: Power cycle the PHY or the whole system?
2. Question is regarding the power sequencing of the system: Does the MAC and PHY come up together?
Reply to TI - 1. Power cycle the whole system.
2. PHY first followed by MAC.
