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xio2001 read performance is serverely declined when using dma transport

liuke liuke
Prodigy 170 points
Other Parts Discussed in Thread: XIO2001

Hi Expert:

   We use a Freescale's P1020 processer in our reference design, which connect TI's XIO2001 via its PCIe controller, and on the
other side of XIO2001(PCI side), we connect a TI's C6416 DSP. The problem is when we use DMA to get data from C6416's L2SRAM to
DDR via XIO2001, the speed is too slow(8.69M/S) but in the reversed direction, the speed is OK(100MB/s).

   Is there anything we can try to improve the performance?

   Thanks

  • 0
    Guru 316690 points

    If the C6416 initiates the transaction, and the data is moved from the C6416 to the P1020, isn't this a write, not a read?

  • 0 in reply to Clemens Ladisch
    Prodigy 170 points
    Thank you for your reply，the dma transaction，is initiated by the p1020. We have another board which almostly the same but use pi7c9x110 as the pcie-to-pci bridge.The same test program on this board shows that the read and write speed both achieve 90MB/S by p1020 initiated the dma transtraction . We had alreadly checked the MAX_PAY_LOAD and READ_SIZE value. Could you give us any other suggestion ? Thanks a lot.
  • 0 in reply to liuke liuke
    Guru 316690 points
    In theory, no optimizations should be required for transactions initiated from the PCI Express bus.

    If I had to guess, I'd suspect that the size of the individual read requests is too small. (Is the DMA configuration of both P1020's the same?)
  • 0 in reply to Clemens Ladisch
    Prodigy 170 points
    thank you very much for your reply,after many tests we found the following informations:

    1.When p1020 initiate a DMA transfer from pci device to local DDR memory,the xio2001 start a brust read but the command code(CBE) is b0110 which means it uses a normal memory read transtraction.
    Owing to brust read, the FRAME signal continue to be valid until the target device assert the STOP signal,here we found only 32 valid bits is transfered.
    We assume that the target device disconnect with Data during every read brust transfer is due to the wrong commond code(CBE).


    2.The PI7C9X110,by comparsion, start a brust read but the command code is b1100 which means it use a memory read multiple transaction and it works all right.

    We run on the linux platform ,both the xio2001 broad and PCI79X110 broad we use the same test code including the kernel,driver,and test app.The DMA configuration is totally the same.
    We wondered why the xio2001 use normal memory read transaction (b0110) in a brust read transfer which doesn't make sense.
    Could you give us any suggestion?

    Thanks a lot.
  • 0 in reply to liuke liuke
    Guru 316690 points

    Section 7.2.2 of the TMS320C6000 PCI Reference Guide (SPRU581) shows that it is indeed the slave that disconnects.

    Anyway, please check the output of "lspci -v" for the bridge and the TMS; is the memory prefetchable or not?

  • 0 in reply to Clemens Ladisch
    Prodigy 170 points
    Thanks very much for your help, the problem has been solved.
    Our problem mainly because we leave the Prefetchable Memory Base Register (0x24) and Prefetchable Memory Limit Register (0x26) as the default value.Our target address is 0x80000000-0x80100000,after change the value of those two registers the transfer speed increasing from 8.7MB/s to 82MB/s and the transtraction command code is memory read multiple (b1100) .Oddly those two registers of PIC79X110 seems no need to configure, just leave the value as the wrong default value but it still works and that mislead us.