Chip: SN65DSI86
1. Related specs: Resolution ratio 1536*2048, eDP interface.
2. Refclk=27Mhz, single mipi interface
Problem: Configue SN65DSI86 though I2C, no problem on I2C read and write, but there is no react of LCD, the interface frequency signal of eDP is too high to catch by my oscilloscpe, so I don't know how to analyze now, the register status of 0xf0-0xf8 is as followed:
Reg(0xf0) = 0x0
Reg(0xf1) = 0x20
Reg(0xf2) = 0x0
Reg(0xf3) = 0x0
Reg(0xf4) = 0x0
Reg(0xf5) = 0x2
Reg(0xf6) = 0x40
Reg(0xf7) = 0x0
Reg(0xf8) = 0x1
the description of the fifth bytes of register f1=0x20:
CHA_INVALID_LENGTH_ERR. When the DSI channel A packet processor detects an invalid transmission length, this bit is set; this bit is cleared by writing a 1 or when the DSIx6 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.
the description of the sixth bytes of register f6=0x40:
LOSS_OF_DP_SYNC_LOCK_ERR. This field is set whenever the DP sync generator has lost lock with the DSI sync stream.
Questions:
1. What is the reason of the above status error flag? And how to solve it?
2. The input MIPI timing sequence is decided by the timing of the back-end screen or the inherent input timing parameters of SN65DSI86?
Thanks a lot!
