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DP83822 operational delay after PWNDW_N deasserted

Pascal REGACHE
Prodigy 240 points
Other Parts Discussed in Thread: DP83822I

Hello, I have selected the DP83822I for a new design.

For power savings reason, I would like to keep the PWNDN_N pin asserted at board power-up.

However, I cannot find in the datasheet the delay from PWNDN_N  de-asserted to chip fully operationnal.
Is it the same as a regular power-up (section 7.6) ?

Also, regarding section 7.7, how can the device be so slow from a RESET_N deassertion when the 83848 took just few micro seconds. Is it a datasheet mistake ?

Thanks

Best regards

Pascal

  • 0
    TI__Mastermind 19780 points
    Hi Pascal,

    I am looking into this for you. Please give me a few days to get an answer.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    TI__Mastermind 19780 points
    Hi Pascal,

    The time required for the PHY to stabilize after RESET_N deassertion is significantly less than the datasheet indicates.

    The T3 value is 3us typ. The T4 value is 150ns typ.

    The value in the DP83822 datasheet will be updated.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 240 points

    Hi Rob,

    Thanks for the clarification about reset time.

    However, my original question is about the startup time from a PWRDN release ? Any data ?

    While the device is in IEEE Pwoer down, there are still active function within teh chip and I am expecting a shorter delay than a regular power up.  

  • 0 in reply to Pascal REGACHE
    Prodigy 240 points
    Hello, how can i get an answer for the PWRDN to chip fully operationnal delay ? This shoumd normally be specified in the component datasheet.
    Thanks
    Pascal
  • 0 in reply to Pascal REGACHE
    TI__Mastermind 19780 points
    Hi Pascal,

    The PWDN signal timing has the same relationship as the RESET pin to MDIO access and activity on the line.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 240 points
    Hello Rob & all, I needd to reopen this thread for further clarification of the DP83822 operation with respect to power down.
    1- My understanding was that MDIO register access is fonctional while in power down state (through PWDN_N pin). Given the previous answers and the lack of datasheet data about PWDN_N operation, I am not quite sure now. So is that correct ?
    2- Do we need an active clock on XI to have register access functional while in power down state ?
    3- With respect to wakeup time from a PWDN_N de-assertion, does the clock state (XI input) makes a difference if that clock is started at the same time as rather tahn having it free running while in power up state (PLL lock) ? The PHYSCR bit 15 casts some doubts about the clock state wile in power down state.

    Thanks
    Best regards
    Pascal