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QuadSGMII to SGMII splitter

Konrad Eisele
Prodigy 120 points

Other Parts Discussed in Thread: DP83867E

Hello everyone,

I am searching for a chip that connects to QuadSGMII on one side and multiple SGMII on the other.
The purpose is to utilize one QuadSGMII serdes  to connect multiple SGMII chips, not a single
4-port QuadSGMII Phy but multiple SGMII Phys. I'm not shure what is should be called but
QuadSGMII to SGMII splitter?
Does anyone know such a chip? Is there such a chip from TI?

// Greetings Konrad 

  • 0
    TI__Mastermind 29655 points
    Hi Konrad,

    I just checked with our Ethernet team, and they responded that they do not have support for an aggregation or de-aggregation device that supports SGMII to dual or quad SGMII.

    We do have aggregators and de-aggregators that are supported by our high-speed team in Dallas (TLK devices), but these devices are primarily used for 1GbE-40GbE transceiever applications.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 120 points

    Hi Michael,

    Ok, thanks for the answer. So I though about another solution then and would
    like to ask weather it might work:

    [cpu]<-qsgmi-serdes->[quad-port-phy] <-rj45-on-board-ethernet->[phy]<-sgmii->[final phy]


    - I connect the QSGMII serdes to a standard quad-port-phy
    - I connect each ethernet port of the quad-port-phy thought
      a on-board RJ45 ethernet network to a single PHY with SGMII output.
    - I connect the SGMII phy to the final SGMII phy.

    The limitation in the system is that I only have one QSGMII serdes but the final phy
    has a SGMII interface.

    The question:
     The final SGMII connection is a Phy<->Phy connection. Is there a change that this
     works in respect to autoconfigure and link-advertisement.... 

    // Thanks Konrad

  • 0 in reply to Konrad Eisele
    TI__Mastermind 29655 points
    Hi Konrad,

    I am not an expert in the QSMGII and SMGII space, so I think it is best to migrate this discussion to the Ethernet forum in hopes that they may have more background about how to answer this question.

    Regards,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    TI__Mastermind 18425 points
    Hi Konrad,

    As I understand it, your concern is about the final stage: [PHY]<----SGMII---->[PHY]
    Theoretically, it should work for auto-negotiation and link advertisement. Speed auto-negotiation and Link Advertisement are not dependent on the MAC configuration. The PHY should be able to auto-negotiate, advertise link, and establish link even if the MAC pins are left floating. SGMII side also performs its own auto-negotiation and configures as per the link speed established on the cable side.

    The ability of a PHY to connect back to back with another PHY over SGMII depends on the design of the PHY so it will be difficult to give a conclusive answer without knowing the exact PHY model and circuit schematic. Is this a TI PHY? The DP83867E/IS/CS can work in this back to back mode.


    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Prodigy 120 points

    Hi Aniruddha Khadye,
    Yes, the answee helped me. It gives me some confidence. The final PHY in the chain 
    is a custom PHY, but I'll consider TI phy for the one inbetween.

    // Greetings Konrad