I have a customer who is seeing the following issue with the DS90CF384 VCC_LVDS as described below:
In all cases the devices are being power at 3.3V for all supplies except the LVDS input supply. There are several supplies on the DS90CF384. One, indicated below, is the power supply pin for the LVDS inputs. We were having problems with LVDS input from an i.MX6 graphics processor into this IC and tried lowering NCC_LVDS voltage to 2.5V as there is some confusion as to the actual differential bias point.
As one reads the datasheet, the only place that references the offset voltage, previously called common mode voltage, or sometimes called the bias or zero point voltage for differential signals, indicates that the values are set to a level that should be compatible with our LVDS driver (see below). That is the datasheet states that the offset voltage should be 1.25V. This would lead one to believe that there is bandgap reference setting this voltage and that VCC_LVDS could safely be 3V3 which is how we designed the part to operate.
However further down in the datasheet the offset appears to be 1.5V. We decided to try and test which offset might be correct by lowering the voltage as there is no way to probe inside the IC and see which might be the case. Interestingly we found that if we power VCC_LVDS at 2.5V (no meaningful lower limiting value is specified for this input) the parts work properly; that is our LVDS signals are received properly and the images appear properly on the display. This kind of makes sense as in many LVDS IC designs, the LVDS bias is derived from the VCC_LVDS. In the 2.5V case 1.25V would be the midpoint for this power input providing differential bias that would be compatible with the driver in the i.MX6. This last statement has the major caveat that our assumptions and interpretation of the results are correct. Checking this assumption is the purpose of the question as the datasheet states no limiting value or recommended operating values for VCC_LVDS other than less than VCC+0.3V and greater than -0.3V.
To test the inverse of course we had already found that when we power at 3V input the LVDS input signaling is corrupted and the displays begin to lose snyc and timing at voltages over 2.95V with a variety of LVDS communications failures appearing at voltages from 2.95V to 3.3V. If the offset derived from 3.3V were to be 1.5V, as indicated below, this would explain the problem as one half of the LVDS (the P side would be almost entirely clipped against the upper rail ).
As I said the devices main circuits are being powered at 3V3 only the LVDS input voltage domain is at 2.5V and if we don’t do this the devices do not work properly with the LVDS driver from the i.MX6 which has a measured nominal DC offset at 1.25V. If our understanding/interpretation of these findings ar incorrect then we have a problem that is difficult to reconcile with measurement and we would greatly appreciate your suggestions as to what the actual problem might be.
We are using the 384 driven by an i.MX6. We have never tested the 383 but I would not be surprised if it doesn’t bias the differential lines to 1.5V given what we have observed. I am thinking that the bias point is one half of VCC_LVDS since the device seems to work robustly when we drop this voltage, but if we are wrong it could be disastrous since this will go into production in a year or so and if we find that part to part variance produces some instances that work and others where it does not.
We have measured the LVDS from the i.MX6 and it is biased at 1.25V +/- some 10s of uV as specified. Please let us know what the designer says, since even though it appears that we have done the correct thing we do need to be certain so as not to end up with a massive warranty situation
Would there be issues in biasing the VCC_LVDS to 2.5V? The data sheet specifies the part using 3.3V. Would the customer possibly see other issues in powering the part this way?
Thanks for your help with this!
Richard Elmquist
