Hello,
We’re observing problems with DS125DF1610 retimers. Under certain conditions the retimers detect signals, but won’t lock until chip is physically reset. Here is the description of software state machine:
- When software starts, it resets the chips and configures all channels to powered-down state (channel register 0x15 bit 3 = 1, register 0x14 bit 6 = 1).
- When SFP module is detected, we reset appropriate channel registers, hold CDR reset, configure the channel to 10G operation and release the CDR reset (just like described in programmer’s guide). Currently we enable DFE to continuous adaptation and adapt mode = 2, but that doesn’t seem to be relevant: same problems are observed with adapt mode 0/1 and DFE disabled.
- Then optical cable is connected to transceiver. At this moment retimer would sometimes lock, but we have channels that wouldn’t lock at all.
- If retimer is locked, and we disconnect a cable, retimer would (naturally) lose the lock. However, when we connect the cable back, retime would never lock!
- After retimer stopped locking, we try to remove SFP module – software would then put channel back to powered-down state (channel register 0x15 bit 3 = 1, register 0x14 bit 6 = 1). Then inserting the module back would trigger the configuration procedure explained in point 2. However, the channel would never lock until the device is restarted (so the chips are physically reset)
- As a remedy we also tried to extend the reset procedure (set all available reset bits in channel register 0) when configuring channel. That didn’t help.
We found a temporary workaround to this problem: we now configure channel to 10G when SFP module is detected AND RX LOSS signal is not present (e.g. cable is connected). When cable is disconnected, we try to power-down the channel ASAP, usually that happens within a few milliseconds. Strangely enough, that helped: all channels are now coming back to life and lock when cable is connected. However we suspect that the problem is not solved and may come into view again. We also have channels connected to the backplane, where presence of signal is dictated by different conditions: FPGA being loaded, etc. So, we would like to understand the root case: does the retime enter any unrecoverable state, under what conditions exactly, and how to bring it out of it? Any registers to read/monitor, or to program in order to prevent that?
Don
