Hi
We have a new development with the DP83867 on board a module connected to an FPGA.
The link is up and fixed at 1G, full duplex
The transmit path from the FPGA -> PHY -> Computer works fine up to the data rate I tested on the desk (~8k packets/second)
However the rx path is unreliable. In the FPGA I receive a large number of RX_ER even at low rates (1 packet/s). Initially I had suspected that the RX clock delay was not being set correctly however regardless of the setting the RX_ER remains.
In addition and more importantly, I can poll the Receiver Error Counter Register (RECR), Address 0x0015 over the MDIO interface and I see the counter incrementing as I send packets. So this would suggest to me that the phy is seeing the errors even before the RGMII interface to the FPGA,
I have looked at a few of the other registers on the MDIO interface but I didn't see anything suspicious, however I may not be looking at the correct registers.
The datasheet does not document what would cause an error in the RECR register or why this would increment. Do you have any documentation about this.?
Is there any other registers I should read that might point to the source of the problem? Any thoughts or pointers would be helpful
Diarmuid
