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DS90UB926 PDB reset pulse

Hi TI,

 I'd like to know a reset(PDB) pulse width spec of DS90UB926. 

According to the latest DS90UB928 DataSheet(SNLS417C), the "PDB Reset Low Pulse" spec is 2.0ms(MIN),

Does the DS90UB926 required the same PDB spec with DS90UB928 ?

     

  • Kobayashi-san,

    This thread has been moved to the High Speed Interface forum for more appropriate support.

    Regards,
  • Hello Toshi

    In normal operation, the PDB pin is held low at powerup until all of the power supplies have stabilized, and it is then raised, which brings the device out of reset mode, and begins the startup procedure for the part.

    If after the device has been operating, you need to reset it, then the PDB line should be brought low for at least 2ms and then brought back up again.
  • Hello Mark, thank you for your help.

    Well, I'd like to confirm the following point,

    - I could not find the 2mS pulse requirement in DS90UB926 datasheet, do youhave a plan to update the data sheet ?

    - I've found that the updated VIL(DS90UB928 DS) is 0.7V (MAX),  is it alos apply to  DS90UB926 VIL ?