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TLK2501 Questions

Richard Elmquist
Mastermind 45250 points
Other Parts Discussed in Thread: TLK2501

My customer is asking the following questions:

I am not having any issues with the TLK2501, but that I am suspecting the board layout leading up to the TLK2501 as the root cause of the poor impedance I am seeing when looking into pin 53 (and 54). 

I am an RF circuit designer by background and my tool of choice for looking into issues like this is with a network analyzer.  For the particular board of concern we have two SMA connectors which lead to the serial receive inputs, DINRXP and DINRXN.  When I hook up the network analyzer I see a very poor return loss, particularly at our chosen data rate. 

I would like to find out a couple of things: 

Do you have any network analyzer s11 measured results from that board which can be shared?  I assume the EVM is layed out well and I would like to see how good that impedance can look.

From the datasheet the input capacitance for the TLK2501 has a max value of 2pF.  Do you have a typical value or any more detailed information I could use for a circuit model?  I typically use Agilent’s ADS RF simulator for circuit analysis and don’t typically work with IBIS models.

Can we help them either with S11 data or with more detailed information in the input capacitance of the part?

Thanks for your help with this!

Richard Elmquist

  • 0
    TI__Genius 16150 points
    Hi Richard,

    Have you tried with different values of capacitance for DINRXP/N?

    Please let me verify with the team if there is S11 data.

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • 0 in reply to Luis Omar Moran
    TI__Mastermind 45250 points

    Luis,

    I think that the customer is just looking for the input capacitance of the DINRXP/N pins. I do not  think that he is necessarily wanting to add any capacitance to the input himself. The data sheet listed a maximum value as 2 pF. What values would they normally see? I know that this is not a good question, but I think he is trying to rationalize what he is seeing. Could additional capacitance cause an issue. It seems that this could cause the losses that he is reporting.

    Let me know if you are able to find any S11 data.

    I need to send the customer something to try and answer his questions.

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Mastermind 45250 points

    Luis,

    Ate there any updates on this issue?

    Please let me know if you have any further questions for me or the customer.

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Genius 16150 points
    Hi Richard,

    I'm pushing to get these data, ASAP I will let you know.

    Thanks,
    Luis
  • 0 in reply to Richard Elmquist
    TI__Genius 16150 points
    Hi Richard,

    Sorry for the delay. From the design team:

    We do not have any S11 data available. Basically, the input capacitance wasn't anything design could control since the package, ESD, and bond-pad size were all fixed.

    Regards,
    Luis
  • 0 in reply to Luis Omar Moran
    TI__Mastermind 45250 points

    Luis,

    Thanks for your response to the questions.

    I will relay this back to the customer.

    Can you also look at these further questions that came in from the customer:

    -Is the CML TX output a symmetric, complementary output regarding the positive and negative TX outputs?  For instance, in an AC coupled topology, looking at the receiver, if a “logic 1” is transmitted, will we see the RX+ signal have a positive offset in regards to the Vterm voltage, and the RX- signal have a negative offset from Vterm voltage.  And vice versa, if a “logic 0” is transmitted, will we see the RX- have a positive offset in regards to Vterm voltage, and the RX+ have a negative offset?  This is what we are seeing in the lab. We just want to verify, because it doesn’t match one of the simulation models that we have.

    -Is there a schematic of the TX output internal to the chip, similar to the block diagram on page 4 of the datasheet, but a little more detailed showing how the RRef resistor is connected to the output stage circuitry?

    -Is there an RX eye mask diagram showing the minimum eye opening requirement at the receiver that we can use to verify whether or not our eye diagram measurements meet the minimum requirements for this device?

    -Is there an optimal termination voltage (Vterm) at the receiver in an ac coupled system with VDD set to 2.5V?  The datasheet gives a range of 1500 to VDD-VID/2 mV, our termination voltage recently changed from 2.0V to 1.7V and I am wondering if it could be contributing to the issues we are seeing, 1.7V is still within range, but I’m wondering if it is not optimal.

    Thanks for your help with these questions.

    Richard Elmquist