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Can ds92lv18 deserializer achieve lock with the REN line pulled low?

Daniel Caplan
Prodigy 60 points

It's not quite clear from the data sheet if the deserializer side can achieve PLL lock with the REN signal pulled low.  I am using the SYNC signal on the serializer side and I don't want random data to be produced at the deserializer outputs when lock occurs. 

Thanks!

  • 0
    TI__Mastermind 29655 points
    Hi Daniel,

    From my understanding of the device, the REN pin acts as an enable pin for the receiver outputs ROUTn and clock RCLK. If REN is high, the deserializer is in normal mode, and if REN is low, then the deserializer outputs are placed in TRI-STATE. This should not impact the ability for the internal PLL to achieve lock to the deserializer input.

    Thanks,

    Michael